ENERGY EFFICIENT CMOS FULL-ADDERS FOR ARTHMETIC APPLICATIONS

Overview
Objective Existing Logic Scheme Pass Transistor logic Complementary Pass Transistor Logic Proposed Logic System Advantages Applications Tools used References

Objective
We proposed the design and performance comparison of Full-Adder cells implemented with alternative logic structure.

The resultant Full-Adders shown to be more efficient on regards of power , area and delay consumption , when compared with the other ones reported previously to build low-power arithmetic modules.

Existing Logic Schemes

Pass transistor
Transistors can be used as switches
g s d

g s d

Pass transistors
Transistors

can be used as switches

g=0 s g=1 s d g=0 s d g=1 s d 1 Input 0 g=0 g=0 d Input g = 1 Output 0 strong 0 g=1 degraded 1 Output degraded 0 strong 1

g s d

g s d

A B F B A
B

F
0

0 1 B

1 0

a) XOR function implemented with pass-transistor circuit. b) Karnaough map showing derivation of the XOR function

Cont.
The PTL is the most popular for Low Power digital circuits. The main advantages of PTL over other traditional CMOS design is I. High speed due to low node capacitance. II. Low power dissipation, as a result of reduced no of transistors.

Cont
Problems in PTL: I. Slow operation at the reduced power supply as the threshold voltage drop across the single channel pass transistor results in low drive current. II. The high input voltage level at the regenerative inverter is not Vdd , the PMOS device in the inverter is not fully turned OFF and hence direct path static power dissipation is significant.

Cont
A=Vdd + V th B=Vdd B A (a) (b) Fmax = Vdd-Vth Cout Vdd Vdd Vdd + V V + th th -Fmax = Vdd-Vth Cout

Threshold voltage drop at the output of the pass-transistor gate

Voltage drop does not exceed Vth when there are multiple transistors in the path

Cont
A=Vdd + V th In=Vdd ON Fmax= Vdd Cout Vdd +Vdd Vdd + V th Cin

Elimination of the threshold voltage drop by: (a) pairing nMOS transistor with a pMOS (b) using a swing-restoring inverter

+
Vdd A=0V (a)

(b)

Complementary Pass Transistor Logic (CPL)

The complexity of full CMOS pass gate logic can be reduced dramatically by adopting another circuit called CPL. The main idea behind CPL is to use a purely NMOS pass transistor network for the operations, instead of CMOS TG(Transmission Gate) network.

Cont
All inputs are applied in complementary form i.e every input signals and its inverse must be provided. The circuit also produces complementary output, to be used by subsequent CPL stages.

Cont

Cont.
Advantages: I. The elimination of PMOS transistors from the pass-gate network significantly reduces the parasitic capacitance associated with each node in the circuit, thus operation speed is typically higher compared to full CMOS counter part .

Proposed System
GDI
GDI(Gate Diffusion Input) is a novel technique for low power digital circuits design in an embedded system. This technique allows reduction in power consumption, delay and area of the circuit.

Cont
This technique can be used to reduce the number of transistors when compared conventional CMOS design. The performance of GDI is compared with CMOS and different other design techniques for several digital circuits.

BASIC GDI CELL

Cont
Some modifications in the standard CMOS inverter derives the basic GDI cell. The sources of NMOS and PMOS are fed by input signals.

GDI cell consists of three input terminals G,P and N.

Cont
In this the source of PMOS is not connected to VDD and the source of NMOS is not connected to GND. This feature gives the GDI cell two extra input pins to use which makes GDI design more flexible than an usual CMOS design. To be more specific the GDI requires twin-well CMOS or silicon on insulator(SOI) to implant.

Cont
The various functions that can be implemented with GDI cell, which consists of only two transistors is as shown below.
S.No N P G Output Function

1.
2. 3. 4. 5. 6.

0
B 1 B C 0

B
1 B 0 B 1

A
A A A A A

AB
A+B A+B AB AB+AC A

F1
F2 OR AND MUX NOT

Tools Used
The DSCH program is a logic editor and simulator which is used to validate the architecture of the logic circuit before the microelectronics design is started. DSCH design entry and simulation software provide a complete and cost effective design solution custom IC design. Tanner Tools.

References
1 . A. Morgenshtein, A. Fish, I.A. Wagner, Gate-Diffusion Input (GDI)- A Power Efficient Method for Digital combinatorial circuits, IEEE Transactions on VLSI Systems, vol.10, no.5, October 2002. 2 . A. Morgenshtein, I. Shwartz, A. Fish, Gate Diffusion Input (GDI) Logic in Standard CMOS Nanoscale Process, 2010 IEEE 26th Convention of Electrical and Engineers in Israel. 3 . S. Fisher, A. Teman, D. Vaysman, A. Gertsman, O.Y.Pecht, A. Fish, UltraLow Power Subthreshold Flip-Flop Design, IEEE International Symposium on Circuits and Systems (ISCAS), 2009. 4 . K.Roy, S.Prasad, Low-Power CMOS VLSI Circuit Design, Wiley India 2009.

Cont
[5]A. M. Shams and M. Bayoumi, Performance evaluation of 1-bit
CMOS adder cells, in Proc. IEEE ISCAS, Orlando, FL, May 1999, vol. 1, pp. 2730. [6] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, A System Perspective. Reading, MA: Addison-Wesley, 1988, ch. 5. [7] K. M. Chu and D. Pulfrey, A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic, IEEE J. Solid-State Circuits, vol. SC-22, no. 4, pp. 528532, Aug.1987. [8] K. Yano, K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, A 3.8 ns CMOS 16 16-b multiplier usingcomplementary passtransistor logic, IEEE J. Solid-State Circuits, vol.25, no. 2, pp. 388395, Apr. 1990. [9] M. Suzuki, M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, A 1.5 ns 32-b CMOS ALUin double passtransistor logic, IEEE J. Solid-State Circuits, vol. 28,no. 11, pp. 11451150, Nov. 1993.