1

By
K. SAI KRISHNA
Assistant Professor
Introduction:
The design of electronic circuits using discrete
components is effective for small circuits. When
circuit complexity is more, more no.of electronic
components are required with more no.of
connections between them. Designing of such
circuits may be critical, time consuming and less
reliable.

To avoid these problems, all the components with
their interconnections are fabricated on the same
chip. Such a circuit is called Integrated Circuit(IC).
2
Classification of Integrated Circuits
Mode of
Operation
Linear
Digital
Process
Involved
Level of
Integration
Package
Integrated Circuits
Monolithic
Hybrid
SSI
MSI
LSI
VLSI
ULSI
DIP
Flat Pack
Metal can pack
Ceramic Chip
Carrier Pack
Thick Film
Thin Film
3
1.Mode of Operation:

According to mode of operation integrated circuits are
classified as digital and linear.

Digital Ics are used to form circuits which have two levels
of voltage (or current ) i.e. high and low.

The circuits like logic gates, counters. Shift registers,
multiplexers, demultiplexers, flip-flops are available in
integrated form using digital Ics.

Linear Ics are equivalent to discrete transistor circuits such
as amplifiers, filters, modulators, frequency multipliers
and so on.

Most commonly used linear IC is operational amplifier
with suitable external components, the op-amp is used in
amplifiers, active filters, integrators, differentiators.
4
2. Process Involved:

According to manufacturing process involved integrated
circuits may be classified as monolithic and hybrid.

In monolithic Ics all components(active and passive) are
formed simultaneously by a diffusion process. Then the
components are interconnected using metalization
process.

In hybrid Ics, passive components such as resistors and
capacitors and the interconnections between them are
formed on an insulating substrate.

Active components such as transistors and diodes, as
well as monolithic integrated circuits, are then
connected to form a complete circuit.
5
Hybrid Ics are classified as thin-film or thick-film,
depending on the method used to form the
resistors, capacitors and related interconnections
on the substrate.

In thin-film Ics, a suitable material is evaporated
on a substrate to form resistors, capacitors and
interconnections.

In thick-film Ics, the resistors, capacitors and
interconnections are etched on the substrate by
silk screening.
6
3.Level of Integration:
C om plexity N um ber of G ates Typical Applications
S m all-scale integration(S S I) Few er than 12 Logic gates &O p-Am ps
M edium -scale integration(M S I) 12 to 99(10
2
- 10
3
) Encoders, decoders, counters,
M ux & D em ux, registers
Large-scale integration(LS I) 100 to 9,999(10
3
- 10
5
) M em ory, M icroprocessors
Very large-scale integration(VLS I) 10,000 to 99,999(10
5
- 10
7
) Advanced m icroprocessors
Large m em ories
U ltra large-scale integration(U LS I) 100,000 to 999,999(10
7
- 10
9
) 64-bit m icroprocessors,
Im age processors
G iga-scale integration(G S I) 1,000,000 or m ore(10
9
- 10
11
)
Tera-scale integration(TS I) (10
12
or m ore)
7
4.Package:
1. protect the chip from mechanical damage and
chemical contamination.
2. provides a completed unit large enough to handle.
3. so that it is large enough for electrical connections to
be made.
Three most common packages for ICs are:






Fig: (a)dual-in-line (DIPS) (most common) (b) flat pack
(c) Metal Can Pack
8
Characteristics Of Logic Families:
1. Fan-out:
The no. of standard loads can be connected
to the output of the gate without degrading
its normal operation.
Sometimes the term loading is used.

2. Fan-in:
The Fan-in of a digital logic gate refers to the
no.of inputs.

3.Power dissipation:
The power needed by the gate.
Expressed in mw.
9
Computing fan-out:
) , min(
IL
OL
IH
OH
I
I
I
I
out Fan =
10
4. Propagation delay:

The average transition-delay time for the
signal to propagate from input to output when
the binary signal changes in value.

5. Noise margin:

The unwanted signals are referred to as noise.
Noise margin is the maximum noise added to
an input signal of a digital circuit that does not
cause an undesirable change in the circuit
output .

11
High-state noise margin: Low-state noise margin:
12
Input-Output conditions for positive-logic
NAND and NOR gates:
NAND gate:

a. If any input is Low, the output is HIGH.
b. If all inputs are HIGH, the output is Low.
13
NOR gate:

X
Y
Z
X Y Z
L L H
L H L
H L L
H H L
a. If any input is HIGH, the output is Low.
b. If all inputs are Low, the output is HIGH.
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Current and Voltage Parameters:
15
Current and Voltage Parameters:
Fig: Currents and Voltages in the two logic states
16
Digital IC Terminology 1. Propagation Delay
A logic signal always experiences a delay going through
a circuit.
The two propagation delay times are defined as:
Propagation
delays.
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2.Speedpower product:
The speed of a logic circuit can be increased, that is,
the propagation delay can be reduced, at the
expense of power dissipation.
The product of propagation delay in seconds and
power dissipation in watts (Joules per second )has
the units of energy i.e. Joules(J).
Speed-Power Product(J)=
Propagation delay (Seconds) X
Power dissipation(Joules/Seconds)
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Example:
For a certain IC family, propagation delay is 10ns with an
average power dissipation of 6mw. What is its speed
power product?

Solution:
The speed power product is given as,
SPP= Propagation delay (Seconds) X
Power dissipation(Joules/Seconds)
= 10ns X 6mw= 60 pico Joules(PJ)
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3.Current Sourcing/Sinking:
Current-sourcing action.
When the output of gate 1 is HIGH, it supplies
current I
IH
to the input of gate 2.
Which acts essentially as a resistance to ground.
The output of gate 1 is acting as a source of
current for the gate 2 input.
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Current Sourcing/Sinking:
Current-sinking action.
Input circuitry of gate 2 is represented as a resistance
tied to +V
CC
the positive terminal of a power
supply.
When gate 1 output goes LOW, current will flow from the
input circuit of gate 2 back through the output resistance of
gate 1, to ground. Circuit output that drives the input of gate
2 must be able to sink a current, I
IL
, coming from that input.
21
Logic Families:
Now a days digital integrated circuits are most commonly
used in the modern digital system. The provide following
advantages:
1. Ics pack a lot of more circuitry in a small package, so
that the overall size of almost any digital system is
reduced.
2. The cost of Ics is very low, which makes them
economical to operate.
3. They have high reliability against failure, so the digital
system needs less repair.

22
Logic Families:
Advantages:

4. Their reduced power consumption makes the digital
system more economical to operate.

5. The operating speed is higher, which makes them
suitable for high-speed operations.

6. The use of Ics reduces the no.of external wiring
connections because many of them are internal to the
package.
23
Digital Logic Families
Based on BJT & MOSFET-Logic families can be classified
broadly according to the technologies they are built with.
In earlier days we had vast number of these technologies,
as you can see in the list below.
DL : Diode Logic.
RTL : Resistor Transistor Logic.
DTL : Diode Transistor Logic.
HTL : High threshold Logic.
TTL : Transistor Transistor Logic.
IIL : Integrated Injection Logic.
ECL : Emitter coupled logic.
MOS : Metal Oxide Semiconductor Logic (PMOS and
NMOS)
24
Feature of BJT
BJT
npn or pnp
Si or Ge
Si is used mainly
npn is most popular
Typical npn Transistor Parameters:

25
Bipolar Junction Transistors
pnp BJT
npn BJT
26
Diode symbol and characteristic
27
Diode-Transistor Logic (DTL)
28
29
1.
2.Diode-Transistor Logic (DTL)
D1 D2
A B C Z
1 1 1 0
0 1 1 1
1 0 1 1
1 1 0 1
DA
DC
DB
I1
I2
Ic
If are reverse biased & the
voltage at the point & transistor goes to
saturation.
If any i/p is low (say A) DA is FB, voltage at
point is 0.2+0.7=0.9 (voltage drops at 0.7
then 0.2+0.7 then the transistor is cut off ).
DA, DB, DC
D1 D2
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Diode-Transistor Logic (DTL)
Advantages:
1. Greater Fan-out.
2. Improved Noise Margin.
Disadvantages:
1. More complex than RTL.
2. Slower Speed.
Characteristics:
1. Power dissipation: 12mw
2. Propagation delay: 30ns
3. Noise Margin: 1v
4. Fan-out is high .
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32
based on bipolar transistors.
one of the most widely used families for small- and
medium-scale devices rarely used for VLSI.
typically operated from 5V supply.
typical noise immunity about 1 1.6 V.
many forms, some optimised for speed, power, etc.
high speed versions comparable to CMOS (~ 1.5 ns)
low-power versions down to about 1 mW/gate.

3. Transistor-transistor logic (TTL)

33
Transistor-transistor logic (TTL)

Most TTL circuits have a similar structure
NAND and AND gates use multiple-emitter
transistor or multiple diode junction inputs.
NOR and OR gates use separate input transistors.
The input will be the cathode of a P-N junction
A HIGH input will turn off the junction.
Only a leakage current is generated.
A LOW input turns on the junction.
Relatively large current is generated.
Most TTL circuits have some type of totem-pole
output configuration.
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Transistor-transistor logic (TTL)
The basic TTL logic circuit is the NAND gate.
Basic TTL
NAND gate.
Diode equivalent
for Q
1
.
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Truth Table
35
TTL NAND gate LOW output
Transistor-transistor logic (TTL)
36
Transistor-transistor logic (TTL)
A TTL output acts as a current sink in the LOW state
because it receives current from the input of the gate that
it is driving.
Q
4
is performing a current-
sinking actionderiving its
current from the input
current (I
IL
) of the load gate.
Q
4
is often called the current-
sinking transistor or pull-
down transistor because
it brings the output voltage
down to its LOW state.
37
TTL NAND gate HIGH output
Transistor-transistor logic (TTL)
1
0
1
38
Transistor-transistor logic (TTL)
A TTL output acts as a current source in the HIGH
statea small reverse-bias leakage current.
Transistor Q
3
is supplying the
input current (I
IH
) required
by Q
1
of the load gate.
Q
3
is often called the current-
sourcing or pull-up transistor.

In more modern TTL series,
the pull-up circuit is made
up of two transistors.
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Advantages of TTL:
1. Low Power Dissipation.
2. High Speed.
3. High Fan-out Capability.
4. High Compatibility with existing systems.
5. Low Cost.
Disadvantages of TTL:
1. Tight Vcc tolerance.
2. Susceptible to power transients.

40
Example:
A two input NAND gate has Vcc= +5v and 1k load
connected to its output. Calculate the output voltage
(a.) When both input are Low
(b.) When both input are High
Solution:
a. When both inputs of NAND gate are Low, the output is
HIGH and it is given as,
VOH= Vcc -VCE(sat)-VD-IL X (130 )
= 5-0.1-0.7-IL(130 )= 4.2v-IL(130 )
Where the load current is,

O
= =
k
V
R
V
I
OH
L
OH
L
1
1
41


v
k
v
V
V
V
V
V
V
OH
OH
OH
OH
OH
OH
716 . 3
1130
4200
4200 1130
2 . 4 ) 130 (
1000
) 130 (
1
2 . 4
= =
=
= O +
O
O
=
Substituting for IL in the eq 1, we get
b. When both inputs of NAND gate are HIGH, the output
is low and it is given as, VOL= VCE(sat) =0.1v
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The TTL gates in all the versions have three different
types of output configurations which are:

(i) TTL NAND gate with Totem-Pole output.
(ii) TTL with Open Collector Output.
(iii) TTL with three state output (or) Tri-State Logic.
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i. Open-collector TTL Gate
44
Operation:
The o/p of the TTL gate is taken from the
open collector of Q3. A resistor connected
to Vcc must be inserted externally to the
IC package for the o/p to pull-up to the
high voltage level when Q3 is off,
otherwise the o/p acts as an open circuit.
If any i/p is low, Base-Emitter junction Q1
is forward biased.
The voltage at the base of Q1 is equal to the
i/p voltage of 0.2v plus a VBE drop 0.7, Q3
start conducting, the path from Q1 to Q3
must over come a potential of one diode
drop in the base collector pn junction of Q1
& two VBE drops in Q2 & Q3.
If all i/ps are high, both Q2 & Q3 conduct & saturate. The base voltage of Q1 is equal
to the voltage across its base collector pn junction plus two VBE drops in Q2 & Q3.
Open-collector TTL Gate
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Applications:
1. Performing wired logic.
2. Constructing a common bus system.

Wired-AND of Two Open-Collector (in TTL)
ii. TTL Gate with Totem-Pole Output
Transistor Q3 & Q4 as a Totem-
Pole because they produce low
output impedance.
Here Q3 acts as a emitter
follower.
When Q3 is conducting, the
output impedance is
approximately 70 ohms.
When Q4 is saturated the
output is only 12 ohms. So the
output impedance is low.
So the output voltage can
change quickly from one state
to the other state.
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TTL Gate with Totem-Pole Output
Advantages:
1. Low Cost.
2. Low Power Dissipation.
3. High Speed.

Disadvantages:
1. In Totem Pole output wired logic connection is
not allowed.
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iii. Three-state TTL Gate
A Three-state gate exhibits three output states:
1. A Low-level state occurs when the lower
transistor in the totem-pole is ON and the upper
transistor is OFF.
2. A High-level state occurs when the upper
transistor in the totem-pole is ON and the lower
transistor is OFF.
3. A Third state occurs when both transistors in
the totem-pole are OFF.
48
Three-state TTL Gate
49
Operation:
When enable i/p is low Q2 is
OFF, the o/p circuit operates a
normal totem pole configuration.
Here o/p state depends on the i/p
state.
When enable i/p is HIGH, Q2 is
ON, Q3 & Q5 are OFF. Here D1 is
forward biased, Q4 is also turns
OFF.
Totem pole transistors (Q4 &
Q3) are OFF, they are effectively
open, and the o/p is completely
disconnected from the internal
circuitry.
Standard TTL Characteristics:
Characteristics Values
Supply Voltage For 74 series (4.75 to 5.25) units
For 54 series (4.5 to 5.5) units
Temperature Range For 74 series (0
0
to 70
0
c

)
For 54 series (-55
0
to 125
0
c

)

Voltage Levels
V
oL(max)
-0.4v, V
oH(max)
-2.4v,
V
IL(max)
-0.8v, V
IH(min)
-2.0v


Noise Margin 0.4v
Power dissipation 10mw per gate
Propagation delay Typically 10ns
Fan-out 10
50
Comparison between Totem-Pole and
Open Collector Output:
Totem Pole Open Collector
1. Output stage consists of
pull-up transistor, Diode
resistor and pull down
transistor.
1. Output stage consists of
only pull down transistor.
2. External pull-up resistor is
not required.
2. External pull-up resistor is
required for proper
operation of gate.
3. Output of two gates
cannot be tied together.
3. Output of two gates can
be tied together using
wired AND technique.
4. Operating speed is high. 4. Operating speed is low.
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4.Emitter-coupled logic (ECL)

52
very fast operation - propagation delays of 1ns or less.
high power consumption, perhaps 60 mW/gate.
low noise immunity of about 0.2-0.25 V.
used in some high speed specialist applications, but
now largely replaced by high speed CMOS.
ECL is a Non saturated operation.
High level -0.8V, Low level -1.8V
Including
Differential input amplifier
Internal temperature and voltage compensated bias
network
Emitter-follower outputs
ECL also called as Currents Mode Logic (CML) or
Current Steering Logic (CSL) or Non-Saturating Logic (NSL).



Emitter-coupled logic (ECL)

53
Emitter-coupled logic (ECL)
Graphic Symbols of ECL Gates
54
Emitter-coupled logic (ECL)
Advantages:
1. Very High Speed.
2. High fan-out capabilities.
3. Low noise margin.
4. Complementary output.

Disadvantages:
1. Difficult to interface with other logic families.
2. High cost.
3. Requiring careful circuit layout.
55
56
Comparison of TTL families
FET
The Field- Effect Transistor (FET) is a unipolar
transistor, since its operation depends on the flow of
only one type of carrier. There are two types of FETs:

1. Junction Field- Effect Transistor (JFET).
2. Metal-Oxide Semiconductor (MOS).

The former is used in linear circuits and the latter in
digital circuits. MOS transistors can be fabricated in less
area than bipolar transistors.
57
MOS AND CMOS ICs
MOS stands for metal-oxide semiconductor.
PMOS, NMOS, and CMOS are three technologies used to
manufacture ICs.
NMOS stands for negative-channel metal-oxide semiconductor.
NMOS ICs are faster than PMOS.
PMOS stands for positive-channel metal-oxide semiconductor.
CMOS stands for complementary metal-oxide semiconductor.
Both PMOS and NMOS devices are used it its manufacture.
CMOS ICs are noted for exceptionally low power consumption.
CMOS ICs were slower than bipolar digital ICs (such as TTL
devices).
Transmission gates or bilateral switches are unique digital devices
created using CMOS technology.
58
Metal Oxide Semiconductor:
MOS technology derives its name from the basic
structure of a metal electrode, over an oxide
insulator, over a semi-conductor substrate.
Transistors of MOS technology are field-effect
transistorscalled MOSFETs.
The electric field on the metal electrode side of the oxide
insulator has an effect on the resistance of the substrate.

Most of the MOS digital ICs are constructed
entirely of MOSFETs and no other components.
MOSFETs are relatively simple and inexpensive
to fabricate, small, and consume very little power.
59
Metal Oxide Semiconductor:
There are presently two general types of MOSFETs
depletion and enhancement.
MOS ICs use enhancement MOSFETs exclusively.


The direction of the arrow indicates either P- or N-channel. The symbols
show a broken line between the source and the drain to indicate there
is normally no conducting channel between these electrodes.
60
MOS Technology Basic MOSFET Switch
An N-channel MOSFET is the
basic element in a family of
devices known as N-MOS.
--Drain is always biased positive
relative to the source.

Gate-to-source voltage V
GS
is the
input voltage.
--Used to control resistance
between drain & source.
--Determines whether the
device is on or off.


61
Metal Oxide Semiconductor: (N-Channel)
Advantages of MOSFET:
1. Their processing is very simple and low cost.
2. Their high input impedance.
3. Their small size and low power dissipation
typically less than 1mw.

Disadvantages:
1. Low operating speed. Their propagation time of
the order of 300nsec.
2. High output impedance.
3. Low current.
4. Special interface circuit are required for TTL
etc.
62
MOS Technology Basic MOSFET Switch
The P-channel MOSFETP-
MOSoperates in the same
manner as the N-channel.
-- Except that it uses
voltages of opposite
polarity.
The drain is connected to the
lower side of the circuit so it is
biased with a more negative
voltage relative to the source.
To turn the P-MOSFET ON, a
voltage lower than the source
by V
T
must be applied to the
gate.
--Voltage at the gate, relative
to the source, must be
negative.

63
Advantages of MOSFET:
1. MOSFETs can be fabricated in less area than
Bipolar transistors and so they are small in size.
2. Increased circuit complexity per package.
3. Low cost per circuit function.
4. Low power drain per function.

Disadvantages:
1. Very low speed.
2. Requiring multiple power source to properly
operate and interface to other logic families.

64
Metal Oxide Semiconductor: (P-Channel)
Complementary MOS Logic CMOS Inverter
P-MOS & N-MOS circuits began to dominate the LSI
and VLSI markets in the 1970s and 1980s.
Use fewer components & are much simpler to
manufacture than TTL circuits.
During this technology the P-MOS & N-MOS
transistors are used in the same circuit.

65
Complementary MOS Logic CMOS Inverter
The CMOS INVERTER has two MOSFETs in series.
The P-channel device source is connected to V
DD
.
The N-channel device has its source connected to
groundusually labeled V
SS
.

Basic CMOS INVERTER.
or
66
Complementary MOS Logic CMOS Inverter
The CMOS INVERTER has two MOSFETs in series.
Gates of the two devices are connected together
as a common input.
Drains are connected together as common output.

Basic CMOS INVERTER.
67
CMOS NAND and NOR gates
68
Tri-State Outputs
69
The third logic state which is not a
state at all. When a output is tri-
stated it looks like a high
impedance to any other device.
Often called floating, or Z state.

Requires an additional control
input, typically called an enable.
The enable controls whether the
output is a LOW or HIGH
(enabled) or Tri-Stated (disabled).

Tri-state outputs are typically used
were multiple outputs share a
signal or bus. For example; data
outputs on memory devices are
tri-state outputs.
Tri-State Buffer
CMOS Open-Drain Outputs
70
In a CMOS device, the PMOS transistor
provides for an active pull-up to Vcc.

In an Open-Drain output, the drain of
the top most NMOS transistor is
connected to the output.

Open-Drain outputs are used
primarily for

Driving LEDs
Driving Multi-Source Buses
Performing Wired Logic

Different from Tri-State. Tri-State is
H/L/Z, Open-Drain is L/Z only.
CMOS Open-Drain Outputs
71
Example: Open Drain NAND
CMOS Series Characteristics - Terms
CMOS ICs provide all TTL logic functions, and
special-purpose functions not provided by TTL.
Terms used when ICs from different families or
series are to be used together or as replacements.
Pin-compatibletwo ICs are pin-compatible
when their pin configurations are the same.
Functionally equivalentICs are functionally
equivalent when the logic functions they perform
are exactly the same.
Electrically compatibleICs are electrically
compatible when they can be connected directly
to each other without special measures to ensure
proper operation.

72
CMOS Series Characteristics IC Series
The oldest CMOS series is the 4000 series by RCA
functionally equivalent to Motorola 14000.
Rarely used in new designs except when a special-
purpose IC is not available in other series.
The 74HC/HCT series has a 10-fold increase in
switching speed, comparable to 74LS devices.
Pin-compatible with, functionally equivalent to
TTL
ICs with the same device number.
The 74AC/ACT series is often referred to as ACL for
advanced CMOS logic.
Functionally equivalent various TTL series, but
not pin-compatible with TTL.

73
CMOS Series Characteristics IC Series
Series 74AHC/AHCT offers a natural migration path
from the HC series to faster, lower-power, low-drive
applications.
Three times faster, with similar noise immunity
to HC without the over- under-shoot problems.
BiCMOS combines the best of bipolar & CMOS
Characteristics are integrated to produce an extremely
low-power, high-speed logic family.
Limited to functions used in microprocessor
and bus interfacing applications.

74
CMOS Series Characteristics Power
When devices using different supply voltages are
interconnected, special measures must be taken.
The 4000/14000 series and 74C series devices operate
with V
DD
values ranging from 3 to 15 V.
74 series ICs operate over a much narrower range
of supply voltagestypically between 2 and 6 V.
Lower-voltage series (2.5 or 3.3 V) are available.

75
CMOS Series Characteristics Power
In general, CMOS devices have greater noise margins
than TTL.
When a CMOS logic circuit is in a static statenot
changingits power dissipation is extremely low.
Ideally suited for applications using battery power.
Power dissipation of a CMOS IC will be very low as
long as it is in a dc condition.
P
D
will increase in proportion to the frequency at which
the circuits are switching states.

76
CMOS Series Characteristics
Power Dissipation:
Each time a CMOS output switches from LOW
to HIGH, a transient charging current must be supplied
to the load capacitance.
Fan-Out:
CMOS inputs have an extremely large resistance
that draws essentially no current from the source.
10
12
Ohms.
Switching Speed:
Although CMOS must drive relatively large load
capacitances, switching speed is somewhat faster.
Due to low output resistance in each state.




77
CMOS Transmission Gate
Behaves like an analog switch.
Conducts in both directions.
Used to enable or inhibit time-varying analog signals.
When CONTROL = 1, conduction occurs
When CONTROL = 0, conduction is inhibited

78
IC Interfacing
Interfacing means connecting output(s) of one
circuit/system to input(s) of another
circuit/system.
The simplest and most desirable interface circuit
between a driver and a load is a direct connection.
Often a direct connection cannot be made due
to a difference in electrical characteristics.
An interface circuit is connected between the
driver and the load, to condition the driver output
signal so it is compatible with requirements of the
load.

79
IC Interfacing
One must consider following important points
while interfacing two circuits or systems:
1. The driver output must satisfy the voltage
and current requirements of the load circuit.
2. The driver and load circuit may require
different power supplies.
80
TTL Driving CMOS
81
CMOS
TTL
( ) ( ) CMOS TTL V
VIH OH
>
( ) ( ) CMOS TTL I
NI IH OH
>
( ) ( ) CMOS TTL I
NI IL OL
>
The fig. Shows a TTL
gate driving N CMOS
gates. For Such an
arrangement to operate
properly the following
conditions are required
to be satisfied:
Fig: A TTL gate driving N CMOS gates
OL
I
OH
I
I IH
I IL
( ) ( ) CMOS TTL V
VIL OL
s
1
2
N
CMOS Driving TTL
82
TTL
CMOS
( ) ( ) TTL CMOS V
VIH OH
>
( ) ( ) TTL CMOS I
NI IH OH
>
( ) ( ) TTL CMOS I
NI IL OL
>
The fig. Shows a CMOS
gate driving N TTL
gates. For Such an
arrangement to operate
properly the following
conditions are required
to be satisfied:
Fig: A CMOS gate driving N TTL gates
OL
I
OH
I
I IH
I IL
1
2
N
( ) ( ) TTL CMOS V
VIL OL
s
CMOS
Advantages of CMOS:
1. Low power consumption.
2. High noise immunity.
3. Fan-out is more.

Disadvantages:
1. Low speed.
2. Greater propagation delay.
83
Comparison of various logic families

84
General characteristics of IC logic families
85
Logic
Family
Basic
Logic
Type
Propagati
on time
per gate
Power
dissipati
on(mw)
Typically
Noise
Margin(v)
Typical
Fan-in
Max
Fan-out
Relative
cost per
gate
RTL +Ve NOR 50 10 0.2 3 4 Medium
DTL +ve
NAND
25 15 0.7 8 8 Medium
TTL +Ve
NAND
10 20 0.4 8 12 Low
CTL +Ve AND 5 50 0.4 5 25 High
ECL +Ve
OR/NOR
0.5 50 0.25 5 25 High
MOS +Ve AND 250 < 1 2.5 10 5 Very Low
CMOS +Ve NOR
& +Ve
NAND
30 0.05 Depends
on VDD
10 100 Low
IIL +Ve NOR 40 < 1 0.35 - 8 Very Low
Thank You


86