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Dan Solarek
CMOS Technology
Complementary MOS, or CMOS, needs both PMOS and NMOS FET devices for their logic gates to be realized The concept of CMOS was introduced in 1963 by Frank Wanlass and Chi-Tang Sah of Fairchild
did not become common until the 1980s as NMOS microprocessors were dissipating as much as 50W and alternative design techniques were needed
MOSFET Transistors
Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are the transistors most widely used in integrated circuits today The name is due to:
the structure of the device - a sandwich of a metal conductor, an oxide insulator, and a semiconductor substrate the way it works - an electric field controls the flow of current through the device
Although early MOSFET transistors used metal for the first layer, current ones use a polysilicon material
a conductive material with somewhat more resistance than a normal conductor and is easier to fabricate
normally on
normally off
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nMOS
pMOS
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nMOS
pMOS
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Prefix
40 74C 74HC 74HCT 74VHC 74VHCT 74AHC 74AHCT 74FCT 74FCT-T
Example
4009 74H04 74HC04 74HCT04 74VHC04 74VHCT04 74AHC04 74AHCT04 74 FCT 04 74 FCT04T
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A TTL load can consume much more sink and source current
up to 4 mA from and HC/HCT output 8 mA from a VHC/VHCT output
CMOS outputs maintain an output voltage within 0.1V of the supply rails, 0 and VCC.
a worst-case VCC=4.5V is used for the table; hence, VOHminC=4.4V
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Sandwich structure of MOS transistor creates capacitor between the gate and substrate
High input capacitance Slows transition time Limits fan-out or switching speed
NMOS dissipates power in low output state CMOS gate only dissipates power when it is changing state
The faster a CMOS gate switches the more power it dissipates, so there is a tradeoff between speed and power 19
Dynamic
Relies on storage of signal the value in a capacitance requires high impedance nodes
NMOS Logic
Negative charge carriers (electrons) Positive biasing voltage at gate
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CMOS Logic
Transistors come in complementary pairs
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CMOS Inverter
CMOS gates are built around the technology of the basic CMOS inverter:
Vdd PMOS
in
in out
out
NMOS
Symbol Circuit 24
VDD
Charge
A
Open
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VDD
A
Discharge
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Since the gate is essentially an open circuit it draws no current, and the output voltage will be equal to either ground or to the power supply voltage, depending on which transistor is conducting.
VDD
VDD
Vin
indeterminant range
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a) b) c)
Circuit schematic for a CMOS inverter Simplified operation model with a high input applied Simplified operation model with a low input applied 29
Notice that VH = 5V and VL = 0V, and that ID = 0A which means that there is no static power dissipation
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The two modes of capacitive discharging and charging that contribute to propagation delay
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On the other hand the high capacitance of CMOS gate inputs means that the capacitive load on a gate driving CMOS gates increases with fan-out.
This increased capacitance limits switching speeds and is a far more significant limit on the maximum fan-out.
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Complementary CMOS
Complementary CMOS logic gates
pMOS pull-up network nMOS pull-down network a.k.a. static CMOS
pMOS pull-up network
inputs output
nMOS pull-down network
Pull-up ON 1 X (crowbar)
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Complementary CMOS
To build a logic gate we need to build two switch networks:
PUN
PDN
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Conduction Complement
Complementary CMOS gates always produce 0 or 1 Ex: NAND gate
Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 A Requires parallel pMOS
B Y
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Compound Gates
Lets take a look at a gate that implements a more complex function
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Compound Gates
Compound gates can do any inverting function Ex: Y = A B +C D
A B (a) C D A B (b) C A (d) D B Y A B (e) C D (f) A B C D Y D B C D
A (c) C A
B C
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Example: O3AI
Y = ( A + B + C) D
A B C D Y D A B C
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