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ARM9

CONTENTS
INTRODUCTION

COMPARISON
ARCHITECTURE

PIPELINING
REGISTERS

INSTRUCTION

INTRODUCTION
A member of the ARM family of general-purpose microprocessors 32-bit ARM and 16-bit Thumb instruction sets ARM debug architecture and includes logic to assist in both hardware and software debug. Both bidirectional and unidirectional connection to external memory systems. five-stage pipeline Harvard architecture The ARM9TDMI processor core implements ARM Architecture V4t

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Support for coprocessors On-chip Coprocessor Interface Allows Floating Point, DSP, Graphics accelerators

Embedded control applications where high performance, low die size and low power are all important

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Decreased heat production and lower overheating risk. Clock frequency improvements. Shifting from a three stage pipeline to a five stage one lets the clock speed be approximately doubled, on the same silicon fabrication process. Cycle count improvements. Key improvements include Faster loads and stores; many instructions now cost just one cycle. This is helped by both the modified Harvard architecture (reducing bus and cache contention) and the new pipeline stages. Exposing pipeline interlocks, enabling compiler optimizations to reduce blockage between stages

ARCHITECTURE

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:: 5-stage pipeline ARM9 organization Fetch The instruction is fetched from memory and place in the instruction pipeline Decode The instruction is decoded and register operands read from the register file There are three operand read ports in the register file, so most ARM instructions can source all their operands in one cycle Execute An operand is shifted and the ALU result generated If the instruction is a load or store the memory address is computed in the ALU

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Buffer/Data Data memory is accessed if required. Otherwise the ALU result is simply buffered for one clock cycle to give the same pipeline flow for all instructions Write-back The results generated by the instruction are written back to the register file, including any data loaded from memory

PERFORMANCE INCREASE
To increase performance, the pipeline of the ARM9TDMI core was reengineered from the three-stage system used by the ARM7TDMI family to five stages Results in much higher clock frequency. reduced cycles per instruction rating of the processor

REGISTERS
32-BIT datapath and associated control logic. datapath contains 31 generalpurpose registers, coupled to a full shifter, Arithmetic Logic Unit, and multiplie At any one time 16 registers are visible to the user Register 15 is the Program Counter (PC) R14 holds the return address after a subroutine call. R13 is used as a stack pointer

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REGISTER ORGANISATION

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STATUS REGISTERS
Current Program Status Register (CPSR). The CPSR holds: four ALU flags (Negative, Zero,Carry, and Overflow) two interrupt disable bits (one for each type of interrupt) a bit to indicate ARM or Thumb execution five bits to encode the current processor mode. Saved Program Status Register (SPSR) that holds the CPSR of the task immediately before the exception occurred.

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FOUR CLASSES OF INSTRUCTIONS


The ARM and Thumb instruction sets can be divided into four broad classes of instruction: Data processing instructions Load and store instructions Branch instructions Coprocessor instructions.

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DATA PROCESSING
Operate on data held in general purpose registers. Of the two source operands, one is always a register The other has two basic forms: An immediate value A register value optionally shifted. Most data processing instructions can perform a shift followed by a logical or arithmetic operation.

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LOAD AND STORE


These instructions come in two main types load or store the value of a single register load and store multiple register values Load and store single register instructions can transfer a 32-bit word, a 16bit halfword and an 8-bit byte between memory and a register Load and store instructions have three primary addressing modes: offset pre-indexed post-indexed

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BRANCH INSTRUCTION
Allowing any data processing or load instruction to change control flow There is a Branch with Link (BL) that allows efficient subroutine calls

BL preserves the address of the instruction after the branch in R14

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COPROCESSOR INSTRUCTIONS
Three types of coprocessor instructions: Coprocessor data processing instructions invoke a coprocessor specific internal operation Coprocessor register transfer instructions allow a coprocessor value to be transferred to or from an ARM register Coprocessor data transfer instructions transfer coprocessor data to or from memory, where the ARM calculates the address of the transfer.

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REFERANCES
arm.com

ARM system on chip architecture by Stephen Bo Furber

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