A Project Synopsis on

DESIGN AND IMPLEMENTATION OF SQUARE & CUBE ALGORITHM USING VEDIC MATHEMATICS

2012-2013

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

BY PRADEEP.S 1ST SEM (M.TECH) VLSI & EMBEDDED SYSTEM

SJB INSTITUTE OF TECHNOLOGY KENGERI, BANGALORE-560060

OVERVIEW
Introduction

Vedic sutras
Block diagram of square algorithm and cube

algorithm
References

INTRODUCTION
Multiplication is an important fundamental function in

arithmetic operations.
The process of raising a number to a power i.e.,

exponentiation is an important operation. The exponentiation operation, like square and cube plays a vital role in communication systems, signal processing applications..

 Squaring and cubing can be performed using ordinary

multipliers, which are scalable but they have a larger delay.

Structure based array implementation are faster but scalability

increases design complexity as well as expense. Moreover, multipliers occupy large area, have long latency and consume considerable power.
Therefore, which offer either of the following design targets-

scalability, re-configurability, high speed, low power consumption, regularity of layout and less area or even a combination of some of these features are to be designed.

 Reducing the time delay and power consumption are very

essential requirements for many applications.

Multiplier based on Vedic Mathematics is one of the fast and low

power multiplier.
In the present work we are using the Vedic sutras to compute the

square and cube of the input number.

To compute square we have made use of the Duplex property of

Urdhava Triyakbyam Sutra.

To find the cube of the number Anurupya Sutra of Vedic

mathematics is used.
This approach of obtaining the square and cube of a number is fast

and it is easy and simple to implement.

VEDIC SUTRAS
Vedic mathematics is mainly based on the 16 sutras

dealing with various branches of mathematics like arithmetic, algebra, geometry etc..

Urdhva tiryakbhyam Sutra

Anurupya Sutra

Block diagram for square architecture

(X1X0)

X1
multiplier

X1

X0

X0
multiplier

multiplier

X12

X1*X0

X02

<<
2X1X0

Let us consider how to obtain the square of a two bit number :(X1X0) X1 X0 X1 X0 P3 P2 P1 P0

Where P0 = D(X0) = X02 P1 = D(X1 X0) = 2*X1*X0 P2 = D(X1) = X12

Implementation of cube algorithm

Block diagram for cube architecture (X1X0)

X1xxx
X1 multiplier X12 X1 X0 X1 X0 multiplier X0

multiplier

multiplier

multiplier

multiplier

X13

X12X0 << <<

X1X02

2 X12X0

+ 3X12X0 + 3X1X02

2X1X02

(X1X0)3

 The algorithm is built using the VERILOG

hardware description language and synthesised in Xilinx and simulated in Modelsim.

REFERENCES
M.Ramalatha, K.Deena Dayalan, P.Dharani, A Novel Time And

Energy Efficient Cubing Circuit Using Vedic Mathematics For Finite Field Arithmetic.
Chandra Mohan Umapathy, High Speed Squarer.

Himanshu Thapliyal, Saurabh Kotiyal and M.B Srinivas, Design and

Analysis of A Novel Parallel Square and Cube Architecture Based On Ancient Indian Vedic Mathematics.
Ramachandran.S,

Kirti.S.Pande

Design,

Implementation

and

Performance Analysis of an Integrated Vedic Multiplier Architecture.