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Korea Univ
rs
5 bits
rt
5 bits
imm
16 bits
Korea Univ
op
6 bits
rs
5 bits
rt
5 bits
imm
16 bits
CLK
25:21
PC'
RD
Instruction Memory
Korea Univ
op
6 bits
rs
5 bits
rt
5 bits
imm
16 bits
Instruction Memory
15:0
module signext(input [15:0] a, output [31:0] y); assign y = {{16{a[15]}}, a}; endmodule
Korea Univ
op
6 bits
rs
5 bits
rt
5 bits
imm
16 bits
010 Zero
ALU
ALUResult
Instruction Memory
SrcB
SignImm
15:0
Sign Extend
Korea Univ
I-Type
op
6 bits
rs
5 bits
rt
5 bits
imm
16 bits
ALU
ALUResult
Instruction Memory
20:16
SrcB
SignImm
15:0
Sign Extend
Korea Univ
CLK A1 A2
20:16
WE3
ALU
RD1 RD2
ALUResult
Instruction Memory
SrcB
A3 WD3
Register File
PCPlus4 SignImm
15:0
Sign Extend
Result
Korea Univ
op
6 bits
rs
5 bits
rt
5 bits
imm
16 bits
ALUControl2:0 010
MemWrite 1 CLK
CLK A1 A2
20:16
WE3
ALU
RD1 RD2
SrcA
Zero ALUResult A
Instruction Memory
20:16
SrcB
A3 WD3
Register File
WriteData
PCPlus4 SignImm
15:0
Sign Extend
Result
Korea Univ
R-Type
op
6 bits
rs
5 bits
rt
5 bits
rd
5 bits
shamt
5 bits
funct
6 bits
RegDst 1
MemtoReg 0
CLK A1 A2 A3 WD3
20:16 15:11
WE3
ALU
RD1 RD2
Zero ALUResult
ReadData
0 1
Instruction Memory
20:16
0 SrcB 1
WriteData
PCPlus4
15:0
Result
10
Korea Univ
rs
5 bits
rt
5 bits
PCSrc
imm
16 bits
RegDst x
MemtoReg x
CLK A1 A2 A3 WD3
20:16 15:11
WE3
ALU
RD1 RD2
ALUResult
ReadData
0 1
Instruction Memory
20:16
0 SrcB 1
WriteData
PCPlus4
15:0
<<2
PCBranch
Result
11
Korea Univ
rs
5 bits
rt
5 bits
rd
5 bits
shamt
5 bits
funct
6 bits
31:26 5:0
MemtoReg
0 PCSrc
0 0 1
CLK A1 A2 A3 WD3
20:16 15:11
0 WE 0 ReadData 0 1
ALU
Instruction Memory
20:16
0 SrcB 1 1
WriteData
RD Data Memory WD
PCPlus4
15:0
<<2
PCBranch
Result
12
Korea Univ
PCSrc
31:26 5:0
CLK A1 A2 A3 WD3
20:16 15:11
CLK WE3 RD1 RD2 Register File 0 WriteReg4:0 1 SrcA Zero WE A RD Data Memory WD ReadData 0 1
ALU
ALUResult
Instruction Memory
20:16
0 SrcB 1
WriteData
PCPlus4
15:0
<<2
PCBranch
Result
13
Korea Univ
Control Unit
Control Unit
Opcode5:0
Main Decoder
Funct5:0
ALUControl2:0
14
Korea Univ
B
N
F2:0 000
A N
B N 3F
Cout
Zero Extend
adder
001
F2
ALU
N Y
+ [N-1] S
N = 32 in 32-bit processor
2
N
F1:0
15
Korea Univ
ALUOp1:0 00
Meaning Add
01
10 11
Subtract
Look at Funct Not Used ALUControl2:0 010 (Add) 110 (Subtract) 010 (Add)
Control Unit
Opcode5:0
Main Decoder
ALUOp1:0 00 X1 1X
1X
ALUOp1:0
100010 (sub)
100100 (and) 100101 (or) 101010 (slt)
16
110 (Subtract)
000 (And) 001 (Or) 111 (SLT)
1X
Funct5:0 ALU Decoder ALUControl2:0
1X 1X
Korea Univ
Op5:0
000000 100011 101011 000100
RegWrite
RegDst
AluSrc
Branch
MemWrite
MemtoReg
ALUOp1:0
R-type lw sw beq
1 1 0
1 0 X X
0 1 1
0 0
0 0 1 0
0 1 X X
10 00 00 01
0
1
Control Unit
Opcode5:0
Main Decoder
ALUOp1:0 00 01 10 11
Funct5:0
ALUControl2:0
17
Korea Univ
PCSrc
31:26 5:0
CLK A1 A2 A3 WD3
20:16 15:11
CLK WE3 RD1 RD2 Register File 0 WriteReg4:0 1 SrcA Zero WE A RD Data Memory WD ReadData 0 1
ALU
ALUResult
Instruction Memory
20:16
0 SrcB 1
WriteData
PCPlus4
15:0
<<2
PCBranch
Result
18
Korea Univ
000000 100011
1 1
1 0
0 1
0 0
0 0
0 1
10 00
101011
000100 001000
0
0 1
X
X 0
1
0 1
0
1 0
1
0 0
X
X
00
01 00
19
Korea Univ
J-Type
op
6 bits
addr
26 bits
PCSrc
31:26 5:0
CLK A1 A2 A3 WD3
20:16 15:11
CLK WE3 RD1 RD2 Register File 0 WriteReg4:0 1 SrcA Zero WE A RD Data Memory WD ReadData 0 1
ALU
ALUResult
Instruction Memory
20:16
0 SrcB 1
WriteData
PCPlus4
15:0
<<2
PCBranch
Result
20
Korea Univ
J-Type
addr
26 bits
PCSrc
31:26 5:0
CLK A1 A2 A3 WD3
20:16
CLK WE3 RD1 RD2 Register File 0 WriteReg4:0 1 SrcA Zero WE A RD Data Memory WD ReadData 0 Result 1
ALU
ALUResult
Instruction Memory
20:16
0 SrcB 1
WriteData
PCJump
15:11
PCPlus4
15:0
SignImm 4
27:0 31:28
Sign Extend
<<2
25:0
<<2
PCBranch
21
Korea Univ
R-type
000000
10
lw
sw beq addi j
100011
101011 000100 001000 000100
1
0 0 1 0
0
X X 0 X
1
1 0 1 X
0
0 1 0 X
0
1 0 0 0
1
X X 0 X
00
00 01 00 XX
0
0 0 0 1
22
Korea Univ
module maindec(input [5:0] op, output memtoreg, memwrite, output branch, alusrc, output regdst, regwrite, output jump, output [1:0] aluop); reg [8:0] controls; assign {regwrite, regdst, alusrc, branch, memwrite, memtoreg, jump, aluop} = controls; always @(*) case(op) 6'b000000: 6'b100011: 6'b101011: 6'b000100: 6'b001000: 6'b000010: default: endcase endmodule
Main Decoder
Funct5:0
ALUControl2:0
module aludec(input [5:0] funct, input [1:0] aluop, output reg [2:0] alucontrol); always @(*) case(aluop) 2'b00: alucontrol <= 3'b010; // add 2'b01: alucontrol <= 3'b110; // sub default: case(funct) // RTYPE 6'b100000: alucontrol <= 3'b010; 6'b100010: alucontrol <= 3'b110; 6'b100100: alucontrol <= 3'b000; 6'b100101: alucontrol <= 3'b001; 6'b101010: alucontrol <= 3'b111; default: alucontrol <= 3'bxxx; // endcase endcase endmodule
controls <= controls <= controls <= controls <= controls <= controls <= controls <=
9'b110000010; // R-type 9'b101001000; // lw 9'b001010000; // sw 9'b000100001; // beq 9'b101000000; // addi 9'b000000100; // j 9'bxxxxxxxxx; // ???
23
Korea Univ
ALU
N Y
A
N
module alu(input [31:0] a, b, input [2:0] alucont, output reg [31:0] result, output zero); wire [31:0] b2, sum, slt; assign b2 = alucont[2] ? ~b:b; assign sum = a + b2 + alucont[2]; assign slt = sum[31];
F2
F2:0
000
Function
A&B
B
N
001
010 011 100 101 110 111
A|B
A+B not used A & ~B A | ~B A-B SLT
Cout
Zero Extend
+ [N-1] S
always@(*) case(alucont[1:0]) 2'b00: result <= a & b2; 2'b01: result <= a | b2; 2'b10: result <= sum; 2'b11: result <= slt; endcase assign zero = (result == 32'b0); endmodule
1
N N
0
N N
2
N
F1:0
24
Korea Univ
PCSrc
31:26 5:0
CLK A1 A2 A3 WD3
20:16 15:11
0 WE 1 ReadData 0 1
ALU
Instruction Memory
20:16
0 SrcB 1 0
WriteData
RD Data Memory WD
PCPlus4
15:0
<<2
PCBranch
Result
25
Korea Univ
In most implementations, limiting paths are: memory (instruction and data), ALU, register file. Thus,
Tc = tpcq_PC + 2tmem + tRFread + 2tmux + tALU + tRFsetup
31:26 5:0
MemtoReg Control MemWrite Unit Branch ALUControl 2:0 Op ALUSrc RegWrite Funct RegDst
PCSrc
CLK A1 A2 A3
0 WE 1 ReadData 0 1
Instruction Memory
20:16
1 0 SrcB 1 0 0 1
ALU
WriteData
RD Data Memory WD
PCPlus4
15:0
WriteReg4:0
<<2
PCBranch
26
Korea Univ
fc = 1/Tc fc = 1/950ps
= 1.052GHz
Assuming that the CPU executes 100 billion instructions to run your program, what is the execution time of the program on a single-cycle MIPS processor?
Execution Time = (#instructions)(cycles/instruction)(seconds/cycle) = (100 109)(1)(950 10-12 s) = 95 seconds
27
Korea Univ