Advanced Encryption Standard For Smart Card Security

Aiyappan Natarajan Kesava R.Talupuru David Jasinski Lilian Atieno

Advisor: Prof. Wayne Burleson

Outline
Motivation System Architecture System Interface Encryption Core Key Scheduling Decryption Core Results Conclusion Future work

Motivation
Security in Smart Cards - Cryptography Applications Identification Cards Credit Cards Algorithms Used Rijndael (Advanced Encryption Standard) DES(Data Encryption Standard) RSA(Ronald, Samir and Adleman)

System Architecture
128 128

Input Controller

Data/Key Reg

Encryption Core

128

External System

Processor

Key Scheduling

128

Output Controller

128

Memory

Decryption Core

Output data (From Enc/Dec core)

Processor Input Controller Interface

clk Reset clk
PC 2

send
Input External System
Rdy_in

rec_data

Processor
Rdy_Out

Controller FSM

FSM

instr

Mux_en Serial I/O 128 Parallel Data

d_k

Reset
128

Data Key

Data/Key Register
clk
128

Processor Encryption Core Interface

clk
PC 2

Processor FSM

instr

clk

encrypt

Reset

Key

Scheduling

128

Key_Out

Encryption Core

Cipher Text
128

clk
128

Input Data

Processor - Output Controller Interface

clk instr PC
2 3

Processor FSM
Reset Output_data Data_rdy Output sent

External System

128

Send_data

Controller FSM

Output data clk

Serial I/O

Encryption Algorithm Flow

Raw Data

Sub Key Key Add Sub Key Substitution Shift Row Mix Column Key Add

Repeat (Round-1) times

ED

Key Add

Shift Row

Substitution

Sub Key

Encryption Core
Plain Text
128

FF clk CT

SB

SR

MC
sel
cntrl

ARK

FF
clk

Sub_bytes (SB) Transformation

Input 8 8 8

S
8 Output 8

S
8

S
8

S
8

S
8

Add Round key (ARK) Operation

State
A B C D

Key
A1 B1 C1 D1

Output
A2 B2 C2 D2

E
I M

F
J N

E1 F1 G1 H1

K L O P

= E2 F2 G2 H2 I1 J1 K1 L1 I2 J2 K2 L2 M1 N1 O1 P1 M2 N2 O2 P2

BLOCK DIAGRAM FOR MIX COLUMN S0,C S1,C S2,C S3,C

Left shift by 1 bit

8h1b

8h1b

8h1b

8h1b

XOR x2 x3 x1 x2 x3 x1 x2 x3 x1 x2 x3 x1

XOR

S0,C

S1,C

S2,C

S3,C

Mix column() Transformation

- Operates on State column-by-column.

- Each column is treated as a four-term polynomial.

-The four bytes in the four rows are used for matrix multiplication in GF(28) as shown below.

S '0,C 02 S '1,C 01 S ' 01 2 ,C S '3,C 03

03 02 01 01

01 03 02 01

01 S 0,C S 01 1,C S for0 c 3 03 2,C 02 S3,C

Shift Rows (SR)

S S S S
0,0

S S S S

0,1

S S S S

0,2

S S S S

0,3

no shift

1,0

1,1

1,2

1,3

2,0

2,1

2,2

2,3

3,0

3,1

3,2

3,3

S S S S

0,0

S S S S

0,1

S S S S

0,2

S S S S

0,3

1,1

1,2

1,3

1,0

2,2

2,3

2,0

2,1

3,3

3,0

3,1

3,2

Encryption Simulations Result

Key Scheduling
486 lines of Verilog code (including 256 lines of a lookup table) Input: 128 bit Key Output: 1408 bit Expanded Key, sent out as four 32 bit keys at a time Process:
Word rotation Look up Tables XOR operations

clk

Block Diagram
Mux_select
clk
128 128 128

Key_In

W_Out
128

Mux_select

128 128

Comb Logic

Decryption Algorithm Flow

Raw Data

Sub Key Key Add Sub Key Inv Shift Substitution Key Add Inv Mix

Repeat (Round-1) times

PT

Key Add

Substitution

Inv Shift

Sub Key

Decryption Core
Cipher 128 Text

key

ARK sel

FF

ISR

128

clk

ISB

ARK FF IMC clk PT

128

Decryption Simulation Results

Hierarchical Representation of the whole system

I/P FSM Processor FSM O/P FSM

Encrypt

Decryption

Key Sched

SB

SR

MC AR

ISB

ISR

IMC IAR

Synthesis with Synopsys

Used a Virginia Tech Academic 0.25 um library (vtvtlib25.db) Input:
module.v files vtvtlib25 library

Output: module_gate.v files

Synopsys at Module Level

Floorplanning with Silicon Ensemble

Input: module_gate.v files and Virginia Tech LEF files Output: module.gds2 files

Sizes of 4 main modules:

Interface Encryption Core Decryption Core Key Schedule 760 um X 760 um 1095 um X 1095 um error in floorplanning 1800 um X 1800 um

Silicon Ensemble (Place & Route)

Cadence Virtuoso (DRC & Extraction)

Conclusions
Hardware Implementation of the Rijndael algorithm using Verilog HDL Functional Verification of the code(1800) with the 384 test vectors for encryption/decryption Synthesis of Verilog Code Area Estimations

Future Work
Optimize the system to accommodate different key and data lengths Delay and Power estimation Optimize the design in synthesis Verify using FPGA

References
Draft of AES - Federal Information Processing Standards Publication, Washington D.C. Kuo, Henry and Ingrid VerbauwhedeArchitectural Optimization for a 1.82Gbits/sec VLSI implementation of the AES Rijndael Algorithm Rankl and W.Effing- Smart Card Handbook, Second Edition, Chichester, England, John Wiley & Sons Ltd.,2000