SAP(Simple As Possible) COMPUTER

Topics
SAP-1 Features Component Blocks Instruction Execution

SAP-1 Features
8-bit wide central data bus.

4-bit wide address bus.

16x8 read/write memory i.e. a RAM having 16 memory

locations each 8-bit wide. Program code cannot be more than 5 instructions. Only addition and subtraction possible and no logical operations can be performed by it. An accumulator and a B register, each of 8-bit length. controller/sequencer unit manages the timing of data flow and activities A binary display unit has 8 LEDs that works as the Output unit for SAP-1.

Topics

Central W-Bus Program counter Input and Memory Address Register(MAR) RAM Instruction Register Accumulator B Register Adder/Subtractor Unit Controller/Sequencer Output Register & Binary Display

W-Bus
The architecture of SAP-1 is that of a basic bus-organized

computer. Bus is a subsystem that transfers data between components inside the computer. Outputs of all the registers directly connected to the central bus (W-Bus) are in tri-state. For transfer of data to be in orderly manner, all the other register outputs are bi-state. It is a collection of 8 parallel wires which work to transfer data depending on the status of the clock pulses.

Program Counter
Indicates where the computer is, in its instruction

sequence. It stores the 4-bit memory address of the next instruction in the program, to be fetched and executed. Also called the instruction pointer. The PC ensures sequential fetching of instructions from the memory unit. Initially reset to 0000, it sends its contents to the MAR through the address lines.

Program Counter (contd.)

Subsequently, increments by 1 to point to the address in

the memory unit that is to be accessed next. On reaching the count of 1111, the PC points to the last instruction in the program and is cleared to 0000 for the next computer run. In the schematic, chip 74LS107 is a dual J-K master slave flip flop, producing the upper 2 address bits. IC 74LS107 produces the lower 2 address bits. IC 74LS126 is a quad three-state normally open switch, giving program a tri-state output.

Input and MAR

MAR is part of the SAP-1 memory.
It contains the address and data switch registers. These switch registers, being a part of the input unit;

allow us to send the 4-bit address and the 8-bit data to the RAM. When an existing instruction is being fetched and executed, the address in the program counter is latched into the MAR. The MAR applies the 4-bit address to the RAM, where a read operation is performed for the given address.

Input and MAR(contd.)

In the schematic, a 74LS173 which is a 4-bit buffer register

serves as a MAR. The pins 1 and 2 of the IC are grounded, converting tristate output into a two state output.

Read/Write Memory
The RAM in the SAP-1 is a 16x8 static TTL.

The program code to be executed and data for SAP1computer

is stored in the RAM. It is an asynchronous RAM, which means that the output data is available as soon as valid address and control signal are applied. RAM receives a 4-bit address from the MAR and a read operation is performed. Thus, the instruction or data word stored in the RAM at that location given by the MAR is placed on the W-bus for use in some other part of the computer. Each IC74189 chip is 16x4 static RAM. Together, they give us a 16x8 read/write memory.

Figure: Layout of a RAM

Instruction Register
Part of the control unit. To fetch the instruction from memory, the memory read

operation is performed. This places the contents of the addressed memory location on the W-bus. The content of the instruction register (the 8-bit data from the RAM) is split into two nibbles. The upper nibble is sent to the controller/sequencer. The lower nibble is a tri-state output that is read on to the W-bus when needed. Two 74LS173 chips; each is a 4-bit tri-state buffer register.

Accumulator
Accumulator is a buffered register that stores one of the

operands for the mathematical operations and also the intermediate results. Gives 8-bit output (tri-state)to the W-bus and another 8bit output data(bi-state) to the adder/subtractor unit. Two chips of 74LS173 comprise the accumulator. Two chips of 74LS126 that are 2 tri-state switches are used to place the accumulator contents on the W-bus when EA input is high.

B Register
A general-purpose buffered register in the SAP-1
It stores the second operand required for the

addition/subtraction operation. A low LB input and a positive clock edge will load the 8bit data from the W-bus into the B-register. Two 74LS173 chips form the B-register, containing the two nibbles of the operand to be added or subtracted from that in the accumulator. Grounding the pins 1 and 2 of both chips produce a 2state output for adder/subtractor.

Adder-Subtractor Unit
SAP can perform only addition and subtraction, done by an

adder-subtractor unit. The SAP-1 uses a 2's compliment adder/subtractor. When Su is low the output is the sum of the two operands:S=A+B When Su is high, the difference of the numbers appears:S=A-B Asynchronous i.e. it does not depend on the clock signal for its operation. B register holds one operand while the other operand is held by the accumulator and the result also.

Controller-Sequencer
Determines what sequence of actions occurs in the

processor at any time. Before a computer run, a low CLR signal is sent to the PC and a high CLR to the instruction register. PC is initialized to 0000 and the instruction register is wiped off of the last instruction. The clock signal CLK is sent to all buffer registers. Synchronizes the operation, ensuring timely execution of activities as all register transfers occur on the positive edge of the common CLK signal.

Fig: serial to parallel conversion

Controller-sequencer(contd.)
By setting different values for the select inputs, the

control unit can determine the directions of data flow around the data paths. Select inputs for Adder-Subtractor unit: The control unit sets the select inputs of the ALU that determine which arithmetic operation is to be carried out. Register Clock Inputs: The control unit provides clock inputs to the data registers, thus determining which registers are loaded at each step of a computation.

Output Register
The output port is the 8-bit output buffer register. Simply

data highways or buses to display the output. When EA is high and LA is low, the next positive clock edge loads the accumulator word into the output register. Two 74LS173 ICs form the output register, driving the binary display which constitutes a row of 8LEDs. Each LED connects to one flip-flop of the output port and this way the binary display shows the contents of the output port.

 SAP1 instruction cycle has 6 T-states. 3 T-states used to fetch the instruction code and 3 T-

states as execution cycles. Not all the instructions in the instruction set require all the six T-states for execution. The unused T-state is marked as No Operation (NOP) cycle. Each T-state is called a machine cycle for SAP1. A ring counter is used to generate a T-state at every falling edge of the clock pulse. The ring counter output is reset after the 6th T-state.

Instruction Set
Memory Reference Instructions:

These instructions use the data stored in the memory. For example: LDA, ADD, SUB.
Non-memory Reference Instructions:

These instructions do not involve the data stored in memory. For example: HLT, OUT. OUT transfers accumulator contents to the output port. A complete instruction all by itself and no memory address is needed to be mentioned because it does not include any data or memory interference.

 HLT stands for halt. This instruction tells the computer to stop processing the data.
HLT instruction marks the end of the program.

HLT instruction is a complete instruction in itself and no memory address or RAM word is needed to be mentioned because it does not include any data or memory interference