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Thermal Oxidation Photolithography Etching Dopant Diffusion Metal Evaporation Electrical Testing
Thermal Oxidation
Silicon is the dominant semiconductor used in integrated circuit processing, in large part due to its ability to form a robust (tough) native oxide. This oxide is used for multiple purposes in the fabrication of ICs:
Diffusion barrier for selectively doping (adding impurities to) silicon Dielectric (insulator) for MOS devices Passivation and protection of the silicon surface
Of particular importance in semiconductor processing is cleanliness. For oxidation, cleanliness must be targeted to the molecular level. A specialized process called the RCA Clean is implemented before oxidation to remove
organic contaminants (oils) trace metals alkali ions (sodium).
Thermal Oxidation
After cleaning with the RCA clean, silicon wafers are placed into a high temperature furnace (900C < T < 1200C) in the presence of oxygen or water where the following reaction occurs:
Si + O2 SiO2
or
Si + 2H2O SiO2 +H2
By controlling temperature and oxidation time precisely, oxide thickness can be predicted and controlled accurately.
ECE444 students performing an oxidation process in a high temperature furnace.
In order to create integrated circuits, the silicon wafer must be doped with impurities (boron and phosphorus are the most common) selectively this is accomplished by removing the oxide in specific areas so the dopants are allowed to diffuse (movement due to high temperature) into the exposed silicon. Selective removal of the oxide is performed using Ultraviolet light (UV) sensitive photoresist (PR) to coat the wafer An alignment/illumination system (mask aligner or stepper) to expose the PR A mask or reticle with desired circuit pattern that only allows the UV light to be transmitted in the shape of the circuit pattern Acid to etch the oxide through openings created in the PR mask by photolithography
But photolithography is binary either the film is exposed or not exposed; there are no shades of gray.
Photolithography
Mask or Reticle:
The mask is tranparent plate of fused silica (high purity glass) with an optically opaque film applied to one surface. A detailed layout of the circuit is created using computer aided design (CAD) software, and this pattern is etched into the opaque film. The etched film on the mask creates the hard copy of the circuit pattern. The mask/reticle is then used to transmit UV light in the pattern of the circuit.
Isometric detail view of the ECE444 CAD layout
Photolithography
PR Application:
Photoresist (an organic polymer sensitive to UV light and resistant to attack by acids) is applied to the oxidized wafer using a photoresist spinner. This process uses centrifugal force from high speed rotation of the wafer. The PR is applied as a small puddle in the center of the wafer. When the wafer spins, the PR spreads out over the wafer due to centrifugal force. After spinning, a uniform layer of PR remains on the surface.
ECE444 student dispensing photoresist onto an oxidized silicon wafer. Note the yellow cast to the picture short wavelength light (green, blue, violet, and ultraviolet) exposes PR, so it has been filtered out of the room light, leaving only red, orange, and yellow to see with!
Photolithography
Alignment and Exposure:
The PR coated wafer is placed into a system (mask aligner or stepper) which allows the mask to be aligned to the wafer. After alignment, the system opens a shutter to allow UV light to illuminate the PR through the mask for a controlled period of time. The PR which is exposed to UV light undergoes a photochemical reaction to make the PR more acidic (indene carboxylic acid is produced).
ECE444 student loading PR coated wafer into an Ultratech 1000WF Step and Repeat Projection Alignment system (also known as a stepper).
Photolithography
Development:
After the wafer is exposed to UV light through the mask, the acidic regions of PR are removed by dipping the wafer into an alkaline (base) developing solution. The acidic PR reacts chemically with the basic developer to form water soluble salts that dissolve in the developer. At this point the mask image can be seen in the PR (remember that the PR was illuminated with UV light through the mask, so only light in the shape of the circuit reaches the PR the rest of the PR did not change!). Note: the image from the mask has only been transferred to the PR. The PR will be used as a mask for etching the underlying oxide in an acid bath.
Etching
The previous steps produced a pattern in the PR layer coating the oxidized wafer. This patterned PR will now be used for selectively etching the oxide areas that are exposed. The patterned, PR coated wafer is placed into a hydrofluoric (HF) acid bath to remove the exposed oxide. HF will react chemically with the oxide to form water soluble products that dissolve in the water used to dilute the acid. When the oxide is etched away, the silicon beneath the oxide can be seen. Fortunately, HF does not react with silicon (this is ideal the HF is selective with regards to the two materials present on the wafer). The PR is then removed, leaving a permanent pattern etched into the oxide.
Oxidized and etched 100mm diameter wafer fabricated in the ECE444 laboratory. Mask level 1 used for photolithography. Purple areas are silicon dioxide, silver areas are exposed silicon.
Dopant Diffusion physics Now for the interesting part - when n-type silicon comes into contact with p-type
silicon. A built-in potential (voltage) develops that must be overcome before current can flow from the n-type to p-type regions. Think of carriers as being able to only move across a flat surface or down a slope. The built in potential is a hill that the carrier can not go up. So in order for the carrier to keep moving, the low part must be pushed up to be level or higher than the top of the hill. In the case of an n-type / p-type junction, the energy to push up the low side comes in the form of a voltage applied to the wafer. The voltage is used to push up the ground on the low side of the hill before current flows from n-type to p-type regions.
But if the voltage is reversed, the energy is used to push the low side lower while keeping the high side at the same height! That means the carrier probably wont ever make it up the higher hill, so it is stuck (no current flows).
Dopant Diffusion physics So when n-type silicon is brought into contact with p-type silicon (a pn junction),
current can flow in only one direction. This is the fundamental semiconductor device a pn junction diode a one way switch for current. The devices used in integrated circuits are specialized combinations of pn junctions. The junctions are formed by the addition of impurity atoms from columns III and V of the periodic table into the silicon wafer through diffusion.
The goal of the dopant predeposition diffusion is to move dopant atoms from a source to the wafer, and then allow the dopants to diffuse into the wafer.
The source of dopant can be in several forms solid (boron nitride and phosphorus oxide ceramic discs), liquid (boron tribromide and POCl3), or gas (diborane or phosphine). In order for the dopants to move into the silicon, they must be given energy, usually in the form of heat. In order for the diffusion to occur in a reasonable time, the temperature must be very high (900C <T<1200). At this temperature the dopant (in the form of an oxide) reacts with the exposed silicon surface to form a highly doped glass. It is from this glass that the dopants can then diffuse into the wafer. The first dopant diffusion in the ECE444 process is a boron diffusion (the wafer is originally doped at a low level with phosphorus). This diffusion forms the first pn junctions selectively on the wafer through the openings in the oxide defined by photolithography.
100mm diameter wafer fabricated in the ECE444 laboratory following boron predeposition, boron drive, and re-oxidation.
ECE444 Process
Phosphorus Diffusion Photolithography Mask 2 Etch Phosphorus Predeposition
ECE444 Process
Electrical contact vias (holes) to silicon Photolithography Mask 4 Etch
Metallization
After all diffusion and oxidation steps are completed, metal is deposited onto the surface of the wafer. This metal is used to wire the devices fabricated in the silicon together. The wafers are put into a large chamber and the air is pumped out of the system. A piece of aluminum located on a tungsten boat in the system is heated to high temperature, causing the aluminum to melt and evaporate. The evaporated aluminum will solidify into a thin film when it touches the silicon wafer.
Thermal evaporation vacuum system used in the ECE444 laboratory. This tool was designed and built for an independent study project.
Metallization
After metallization, the wafer is completely covered by the aluminum. It must be patterned and etched to form the actual wires connecting individual devices into a circuit.
Completed wafer
Steps to create ECE444 wafer:
1. Initial oxidation 2. Photolithography Mask 1 3. Oxide etch 4. Boron predep 5. Boron drive and reoxidation 6. Photolithography Mask 2 7. Oxide etch 8. Phosphorus predeposition 9. Photolithography Mask 3 10. Gate oxidation 11. Photolithography Mask 4 12. Etch 13. Photolithography Mask 5 14. Metal evaporation 15. Metal definition
Testing
After completion of the wafer, it must be tested to verify operation. The devices fabricated are extremely small (some dimensions are as small a 1micrometer!), so specialized probes are used to make electrical contact. Once contact is made, several different instruments are used to measure electrical performance.
Silicon Manufacturing
HISTORY
19th Century - Solid-State Rectifiers 1907 - Application of Crystal Detector in Radio Sets 1947 - BJT Constructed by Bardeen and Brattain 1959 Integrated Circuit
a) Oxide Growth & Deposition b) Oxide Removal c) Other effects d) Local Oxidation
4. Diffusion & Ion Implantation
FABRICATING SILICON
Quartz, or Silica, Consists of Silicon Dioxide Sand Contains Many Tiny Grains of Quartz Silicon Can be Artificially Produced by Combining Silica and Carbon in Electric Furnice Gives Polycrystalline Silicon (multitude of crystals)
CRYSTAL GROWTH
Czochralski Process is a Technique in Making Single-Crystal Silicon A Solid Seed Crystal is Rotated and Slowly Extracted from a Pool of Molten Si Requires Careful Control to Give Crystals Desired Purity and Dimensions
CYLINDER OF MONOCRYSTALLINE
The Silicon Cylinder is Known as an Ingot Typical Ingot is About 1 or 2 Meters in Length Can be Sliced into Hundreds of Smaller Circular Pieces Called Wafers Each Wafer Yields Hundreds or Thousands of Integrated Circuits
WAFER MANUFACTURING
The Silicon Crystal is Sliced by Using a Diamond-Tipped Saw into Thin Wafers Sorted by Thickness Damaged Wafers Removed During Lapping Etch Wafers in Chemical to Remove any Remaining Crystal Damage Polishing Smoothes Uneven Surface Left by Sawing Process
Photolithography
Photolithography is a technique that is used to define the shape of micro-machined structures on a wafer.
Photolithography Photoresist
The first step in the photolithography process is to develop a mask, which will be typically be a chromium pattern on a glass plate. Next, the wafer is then coated with a polymer which is sensitive to ultraviolet light called a photoresist. Afterward, the photoresist is then developed which transfers the pattern on the mask to the photoresist layer.
Photolithography Photoresist
There are two basic types of Photoresists Positive and Negative.
Positive resists.
Positive resists decomposes ultraviolet light. The resist is exposed with UV light wherever the underlying material is to be removed. In these resists, exposure to the UV light changes the chemical structure of the resist so that it becomes more soluble in the developer. The exposed resist is then washed away by the developer solution, leaving windows of the bare underlying material. The mask, therefore, contains an exact copy of the pattern which is to remain on the wafer.
Photolithography Photoresist
Negative resists
Exposure to the UV light causes the negative resist to become polymerized, and more difficult to dissolve. Therefore, the negative resist remains on the surface wherever it is exposed, and the developer solution removes only the unexposed portions. Masks used for negative photoresists, therefore, contain the inverse (or photographic "negative") of the pattern to be transferred.
Photolithography Model
Figure 1a shows a thin film of some material (eg, silicon dioxide) on a substrate of some other material (eg, a silicon wafer). Photoresist layer (Figure 1b )
Ultraviolet light is then shone through the mask onto the photoresist (figure 1c).
A chemical (or some other method) is then used to remove the oxide where it is exposed through the openings in the resist (figure 1e).
Finally the resist is removed leaving the patterned oxide (figure 1f).
The patterns on the 5X reticle are reduced 5 times when projected onto the wafer. This means the dies on the photomask are 5 times larger than they are on the final product. There are other kinds of reduction reticles (2X, 4X, and 10X), but the 5X is the most commonly used. Reduction reticles are used on a variety of steppers, the most common being ASM, Canon, Nikon, and GCA.
Photolithography Patterning
The last stage of Photolithography is a process called ashing. This process has the exposed wafers sprayed with a mixture of organic solvents that dissolves portions of the photoresist . Conventional methods of ashing require an oxygen-plasma ash, often in combination with halogen gases, to penetrate the crust and remove the photoresist. Usually, the plasma ashing process also requires a follow-up cleaning with wet-chemicals and acids to remove the residues and nonvolatile contaminants that remain after ashing. Despite this treatment, it is not unusual to repeat the "ash plus wet-clean" cycle in order to completely remove all photoresist and residues.
SiO2 growth is a key process step in manufacturing all Si devices - Thick ( 1m) oxides are used for field oxides (isolate devices from one another ) - Thin gate oxides (100 ) control MOS devices - Sacrificial layers are grown and removed to clean up surfaces The stability and ease of formation of SiO2 was one of the reasons that Si replaced Ge as the semiconductor of choice.
The simplest method of producing an oxide layer consists of heating a silicon wafer in an oxidizing atmosphere.
Deposited Oxides
Oxide is frequently employed as an insulator between two layers of metalization. In such cases, some form of deposited oxide must be used rather than the grown oxides. Deposited oxides can be produced by various reactions between gaseous silicon compounds and gaseous oxidizers. Deposited oxides tend to possess low densities and large numbers of defect sites. Not suitable for use as gate dielectrics for MOS transistors but still acceptable for use as insulating layers between multiple conductor layers, or as protective overcoats.
Oxidizing species
- wet oxidation is much faster than dry oxidation
Surface cleanliness
- metallic contamination can catalyze reaction - quality of oxide grown (interface states)
Etching
Etching is the process where unwanted areas of films are removed by either dissolving them in a wet chemical solution (Wet Etching) or by reacting them with gases in a plasma to form volatile products (Dry Etching). Resist protects areas which are to remain. In some cases a hard mask, usually patterned layers of SiO2 or Si3N4, are used when the etch selectivity to photoresist is low or the etching environment causes resist to delaminate.
Disadvantages
Inability to produce differently doped areas in different parts of the wafer. The thickness and planarity of grown junctions are difficult to control. Repeated counterdopings degrade the electrical properties of the silicon.
Ion Implantation
A particle accelerator is used to accelerate a doping atom so that it can penetrate a silicon crystal to a depth of several microns
Lattice damage to the crystal is then repaired by heating the wafer at a moderate temperature for a few minutes. This process is called annealing.
Ion
References
The Art of Analog Layout by Alan Hastings 2001 Prentice-Hall
Semiconductor Devices by Mauro Zambuto 1989 McGraw-Hill Semiconductor Manufacturing Technology by Quirk and Serda 2001 Prentice-Hall
Objectives this chapter, you will be able to: After studying the material in
1. Describe the current economic state and the technical roots of the semiconductor industry. 2. Explain what is an integrated circuit (IC) and list the five circuit integration eras. 3. Describe a wafer, including how it is layered and describe the essential aspects of the five stages of wafer fabrication. 4. State and discuss the three major trends associated with improvement in wafer fabrication. 5. Explain what is a critical dimension (CD) and how Moores law predicts future wafer fabrication improvement. 6. Describe the different eras of electronics since the invention of the transistor up to modern wafer fabrication. 7. Discuss different career paths in the semiconductor industry.
Microprocessor Chips
Vacuum Tubes
Photo 1.2
Production Tools
Utilities Materials & Chemicals Metrology Tools
Chip Manufacturer
Analytical Laboratories
Technical Workforce Colleges & Universities
Figure 1.1
Figure 1.2
Circuit Integration
Integrated Circuits (IC)
Microchips, chips Inventors Benefits of ICs
Integration Eras
From SSI to ULSI 1960 - 2000
Figure 1.3
Table 1.1
ULSI Chip
IC Fabrication
Silicon
Wafer Wafer Sizes Devices and Layers
1992 1987
1981
1975
1965
50 mm
100 mm
125 mm
150 mm 200 mm
300 mm
Figure 1.4
Conductive layer
Metal layer
Insulation layers
drain
Silicon substrate
Silicon substrate
Figure 1.5
Stages of IC Fabrication
Single crystal silicon 1.
2.
3.
Test/Sort includes probing, testing and sorting of each die on the wafer.
Defective die
Figure 1.6
1. Crystal Growth
6. Edge Rounding
Heater
5. Wafer Slicing
Wafer Fab
Figure 1.8
Semiconductor Trends
Increase in Chip Performance
Critical Dimension (CD) Components per Chip Moores Law Power Consumption
Critical Dimension
Common IC Features
Line Width Contact Hole Space
Figure 1.9
Past and Future Technology Nodes for Device Critical Dimension (CD)
1988 CD (m) 1.0 1992 0.5 1995 0.35 1997 0.25 1999 0.18 2001 0.15 2002 0.13 2005 0.10
Table 1.2
1997 1999 2001 2003 2006 2009 2012 Year Redrawn from Semiconductor Industry Association, The National Technology Roadmap for Semiconductors, 1997. Figure 1.10
100M
Moores Law for The number of transistors on a chip double every 18 months. Microprocessors
500
Pentium
10M
Pentium Pro
1M
80386
80486
25
100K
8086
80286
1.0
10K
8080 4004
.1
1975
1980
1985 Year
1990
1995
.01 2000
Used with permission from Proceedings of the IEEE, January, 1998, 1998 IEEE Figure 1.11
Figure 1.12
0 1997 1999 2001 2003 Year Redrawn from Semiconductor Industry Association, National Technology Roadmap, 1997
Figure 1.13
2006
2009
2012
500 400
300
1976
1980
1984
1988
1992
1996
2000
Year
Figure 1.14
10-8
10-10 1930
1940
1950
1980
1990
2000
Redrawn from C. Chang & S. Sze, McGraw-Hill, ULSI Technology, (New York: McGraw-Hill, 1996), xxiii. Figure 1.15
$1,000,000,000
$100,000,000
1970 $10,000,000
1980
1990
2000 Year
2010
2020
Used with permission from Proceedings of IEEE, January, 1998 1998 IEEE
Figure 1.16
Maintenance Supervisor
Production Supervisor
Process Engineer
BS
Equipment Engineer
Associate Engineer
BSET*
Equipment Technician
AS+
Process Technician
Lab Technician
AS HS +
Production Operator
HS Educatio n
Figure 1.17
Rework
9 6 3
Production Equipment
Inspectio n
Production Equipment
Inspectio n
Inspectio n
Time Out
Wafer Starts
1 2 3 4 6 7 8 9 10 11
Wafer Moves
Wafer Outs
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
12 13 14 15 16 17 18
19 20 21 22 23 24 25
26 27 28 29 30 31
Production Equipment
Inspectio n
Production Equipment
Inspectio n
Production Equipment
Inspectio n
30 31
Production Cycle Time = (Date and Time of Wafer Start) - (Date and Time of Wafer Out) Wafer Outs = Wafer Starts - Wafers Scrapped Operator Efficiency = Theoretical Cycle Time / Actual Cycle Time
Figure 1.18
IC Fabrication An Introduction
Integrated circuit showing memory blocks, logic and input/output pads around the periphery
IC device
drain
Silicon chip
Semiconductor Applications
3C : Computer--- /Communication / Consumables
Types of Chips
Dynamic Random Access Memory chips (DRAMs) - serve as the primary memory for
computers
Programmable memory chips (EPROMs, EEPROMs, and Flash) - are used to perform
Photomask Creation
The photomask is a copy of the circuit pattern, drawn on a glass plate coated with a metallic film. The glass plate lets light pass, but the metallic film does not. Due to increasingly high integration and miniaturization of the pattern, the size of the photomask is usually magnified four to ten times the actual size.
Wafer Fabrication
A high-purity, single-crystal silicon called "99.999999999% (eleven-nine)" is grown from a seed to an ingot. The wafers are generally available in diameters of 150 mm, 200 mm, or 300 mm, and are mirrorpolished and rinsed before shipment from the wafer manufacturer.
Deposition
the wafer is placed in a high-temperature furnace to make the silicon react with oxygen or water vapor, and to develop oxide films on the wafer surface (thermal oxidation). To develop nitride films and polysilicon films, the chemical vapor deposition (CVD) method is used, in which a gaseous reactant is introduced to the silicon substrate, and chemical reaction produce the deposited layer material. The metallic layers used in the wiring of the circuit are also formed by CVD, spattering (PVD: physical vapor deposition)
Photoresist Coating
A resin called "photoresist" is coated over the entire wafer. (~1m thick coating.) Photoresist is a special resin similar in behavior to photography films that changes properties when exposed to light.
Masking/Exposure
Placed over the photoresist-coated wafer, which is then irradiated to have the circuit diagram transcribed onto it. An irradiation device called the "stepper" is used to irradiate the wafer through the mask with ultraviolet (UV) light.
Patterning: Development
The photoresist chemically reacts and dissolves in the developing solution, only on the parts that were not masked during exposure (positive method). Development is performed with an alkaline developing solution. After the development, photoresist is left on the wafer surface in the shape of the mask pattern.
Etching
"Etching" refers to the physical or chemical etching of oxide films and metallic films using the resist pattern as a mask. Etching with liquid chemicals is called "wet etching" and etching with gas is called "dry etching".
Photoresist Stripping
The photoresist remaining on the wafer surface is no longer necessary after etching is complete. Ashing by oxygen plasma or the likes is performed to remove the residual photoresist.
Transistor Formation
A transistor is a semiconductor device with a switching function and three terminals: source, drain, and gate. An insulation layer called "gate oxide" is first formed on the wafer surface. A polysilicon film is deposited onto the gate oxide, and a polysilicon gate for controlling the flow of electrons between the source region and the drain region is formed by lithography and etching. After the polysilicon gate is formed, an ntype diffusion layer consisting of both the source and the drain regions is formed by implantation of impurities
Metallization
Interconnecting the devices, such as transistors, formed on the silicon wafer completes the circuit. the wafer is first covered with a thick and flat interlayer insulation film (oxide film). Next, contact holes are drilled by lithograph and etching, through the interlayer insulation film, above the devices to be connected.
Wafer Inspection
Each IC on the completed wafer is electronically tested by the tester. After this inspection, the front-end processing is complete.
Dicing
In back end processing, a wafer completed in front end processing is cut into individual IC chips and encapsulated into packages.
Mounting
After the IC chips are cut apart, they are sealed into packages. The IC chips must first be attached to a platform called the "lead frame.
Wire bonding
The mounted IC chips are connected to the lead frames.
Encapsulation
The IC chips and the lead frame islands are encapsulated with molding resin for protection.
Characteristic Selection
The packaged IC chips are tested and selected.