You are on page 1of 144

Theory and Fabrication of Integrated Circuits

Where students create integrated circuits from scratch

Thermal Oxidation Photolithography Etching Dopant Diffusion Metal Evaporation Electrical Testing

Thermal Oxidation
Silicon is the dominant semiconductor used in integrated circuit processing, in large part due to its ability to form a robust (tough) native oxide. This oxide is used for multiple purposes in the fabrication of ICs:
Diffusion barrier for selectively doping (adding impurities to) silicon Dielectric (insulator) for MOS devices Passivation and protection of the silicon surface

Of particular importance in semiconductor processing is cleanliness. For oxidation, cleanliness must be targeted to the molecular level. A specialized process called the RCA Clean is implemented before oxidation to remove
organic contaminants (oils) trace metals alkali ions (sodium).

Thermal Oxidation
After cleaning with the RCA clean, silicon wafers are placed into a high temperature furnace (900C < T < 1200C) in the presence of oxygen or water where the following reaction occurs:

Si + O2 SiO2

or
Si + 2H2O SiO2 +H2
By controlling temperature and oxidation time precisely, oxide thickness can be predicted and controlled accurately.
ECE444 students performing an oxidation process in a high temperature furnace.

Photolithography and Etching


After oxidation, the silicon wafer is completely covered with silicon dioxide. This oxide will prevent dopants from reaching the underlying silicon wafer.

In order to create integrated circuits, the silicon wafer must be doped with impurities (boron and phosphorus are the most common) selectively this is accomplished by removing the oxide in specific areas so the dopants are allowed to diffuse (movement due to high temperature) into the exposed silicon. Selective removal of the oxide is performed using Ultraviolet light (UV) sensitive photoresist (PR) to coat the wafer An alignment/illumination system (mask aligner or stepper) to expose the PR A mask or reticle with desired circuit pattern that only allows the UV light to be transmitted in the shape of the circuit pattern Acid to etch the oxide through openings created in the PR mask by photolithography

Photolithography and Etching


Photolithography is very much like taking a picture: PR coated wafer = film Mask aligner or stepper = camera Mask or reticle = subject of the picture

But photolithography is binary either the film is exposed or not exposed; there are no shades of gray.

Photolithography
Mask or Reticle:
The mask is tranparent plate of fused silica (high purity glass) with an optically opaque film applied to one surface. A detailed layout of the circuit is created using computer aided design (CAD) software, and this pattern is etched into the opaque film. The etched film on the mask creates the hard copy of the circuit pattern. The mask/reticle is then used to transmit UV light in the pattern of the circuit.
Isometric detail view of the ECE444 CAD layout

CAD full adder layout

Photolithography
PR Application:
Photoresist (an organic polymer sensitive to UV light and resistant to attack by acids) is applied to the oxidized wafer using a photoresist spinner. This process uses centrifugal force from high speed rotation of the wafer. The PR is applied as a small puddle in the center of the wafer. When the wafer spins, the PR spreads out over the wafer due to centrifugal force. After spinning, a uniform layer of PR remains on the surface.

ECE444 student dispensing photoresist onto an oxidized silicon wafer. Note the yellow cast to the picture short wavelength light (green, blue, violet, and ultraviolet) exposes PR, so it has been filtered out of the room light, leaving only red, orange, and yellow to see with!

Photolithography
Alignment and Exposure:
The PR coated wafer is placed into a system (mask aligner or stepper) which allows the mask to be aligned to the wafer. After alignment, the system opens a shutter to allow UV light to illuminate the PR through the mask for a controlled period of time. The PR which is exposed to UV light undergoes a photochemical reaction to make the PR more acidic (indene carboxylic acid is produced).

ECE444 student loading PR coated wafer into an Ultratech 1000WF Step and Repeat Projection Alignment system (also known as a stepper).

Photolithography
Development:
After the wafer is exposed to UV light through the mask, the acidic regions of PR are removed by dipping the wafer into an alkaline (base) developing solution. The acidic PR reacts chemically with the basic developer to form water soluble salts that dissolve in the developer. At this point the mask image can be seen in the PR (remember that the PR was illuminated with UV light through the mask, so only light in the shape of the circuit reaches the PR the rest of the PR did not change!). Note: the image from the mask has only been transferred to the PR. The PR will be used as a mask for etching the underlying oxide in an acid bath.

Etching
The previous steps produced a pattern in the PR layer coating the oxidized wafer. This patterned PR will now be used for selectively etching the oxide areas that are exposed. The patterned, PR coated wafer is placed into a hydrofluoric (HF) acid bath to remove the exposed oxide. HF will react chemically with the oxide to form water soluble products that dissolve in the water used to dilute the acid. When the oxide is etched away, the silicon beneath the oxide can be seen. Fortunately, HF does not react with silicon (this is ideal the HF is selective with regards to the two materials present on the wafer). The PR is then removed, leaving a permanent pattern etched into the oxide.

Oxidized and etched 100mm diameter wafer fabricated in the ECE444 laboratory. Mask level 1 used for photolithography. Purple areas are silicon dioxide, silver areas are exposed silicon.

Dopant Diffusion physics


Silicon is a column IV element this means there are four electrons in the outermost shell of the atom. It is these electrons that are used when bonding to other atoms. In a wafer, each silicon atom bonds to four other silicon atoms (each Si-Si bond shares one electron). So in an intrinsic (pure) silicon wafer, all the electrons in the outer shell are part of a bond they are stuck between the bonded silicon atoms. In order for current to flow in a material there must be loose electrons. But all the electrons in silicon are working at holding the atoms together, which means it is not a good conductor of current. So what can be done to allow the silicon to conduct current more easily? Free carriers of current must be added. The goal is to find an element about the same size as a silicon atom so that it fits together well with the silicon, but with more electrons in its outer shell.

Dopant Diffusion physics


In the periodic table, the closer elements are to each other, the more similar they are. So the best candidates would come from column V (which have five outer shell electrons). The element closest to silicon in column V is phosphorus. If phosphorus is inserted into the silicon wafer in a certain way, it will take the place of a silicon atom and bond with its four neighbor silicon atoms. After bonding, phosphorus has an electron left over that is not bonded to a silicon atom. It turns out this extra electron is not strongly held by the phosphorus atom any more, so it can be removed easily. This electron then becomes a carrier for current it is free to move around the wafer. So the conductivity of the silicon wafer increases. This type of silicon doped with phosphorus is called an n-type semiconductor.

Dopant Diffusion physics


Extending this idea of inserting an element with a different number of valence electrons, a column III element (such as boron) could be added to the silicon wafer. In this case, the boron will try to bond with four silicon atoms, but it only has three electrons to bond with. This means there is an incomplete bond with one of the silicon atoms a hole where an electron would normally be. This hole behaves much like an electron and can move around the wafer, but with an opposite charge (+). So a different type of current carrier is present in the wafer that increases the wafers conductivity. This type of silicon doped with boron is called a ptype semiconductor. By adding impurities to silicon, the conductivity increases. This conductivity can be adjusted by the amount of impurity added.

Dopant Diffusion physics Now for the interesting part - when n-type silicon comes into contact with p-type
silicon. A built-in potential (voltage) develops that must be overcome before current can flow from the n-type to p-type regions. Think of carriers as being able to only move across a flat surface or down a slope. The built in potential is a hill that the carrier can not go up. So in order for the carrier to keep moving, the low part must be pushed up to be level or higher than the top of the hill. In the case of an n-type / p-type junction, the energy to push up the low side comes in the form of a voltage applied to the wafer. The voltage is used to push up the ground on the low side of the hill before current flows from n-type to p-type regions.

But if the voltage is reversed, the energy is used to push the low side lower while keeping the high side at the same height! That means the carrier probably wont ever make it up the higher hill, so it is stuck (no current flows).

Dopant Diffusion physics So when n-type silicon is brought into contact with p-type silicon (a pn junction),
current can flow in only one direction. This is the fundamental semiconductor device a pn junction diode a one way switch for current. The devices used in integrated circuits are specialized combinations of pn junctions. The junctions are formed by the addition of impurity atoms from columns III and V of the periodic table into the silicon wafer through diffusion.

The goal of the dopant predeposition diffusion is to move dopant atoms from a source to the wafer, and then allow the dopants to diffuse into the wafer.

Dopant Diffusion Predep

The source of dopant can be in several forms solid (boron nitride and phosphorus oxide ceramic discs), liquid (boron tribromide and POCl3), or gas (diborane or phosphine). In order for the dopants to move into the silicon, they must be given energy, usually in the form of heat. In order for the diffusion to occur in a reasonable time, the temperature must be very high (900C <T<1200). At this temperature the dopant (in the form of an oxide) reacts with the exposed silicon surface to form a highly doped glass. It is from this glass that the dopants can then diffuse into the wafer. The first dopant diffusion in the ECE444 process is a boron diffusion (the wafer is originally doped at a low level with phosphorus). This diffusion forms the first pn junctions selectively on the wafer through the openings in the oxide defined by photolithography.

ECE444 Diffusion furnace

Dopant Diffusion - Drive


After the predeposition diffusion the dopants are situated close to the surface of the wafer. However, they must diffuse even farther to lower the overall concentration in order for some of the devices to work properly. The first diffusion (predeposition) introduces dopants into the wafer. The second diffusion (drive) redistributes the dopants and allow the dopants to diffuse into the wafer more deeply (up to ~3 micrometers) In addition, oxygen and water vapor are introduced during the drive diffusion to grow a new oxide over the areas which were exposed to bare silicon during the photolithography process. This new oxide can be patterned again so that other selective diffusion processes can be performed to create other types of devices.

100mm diameter wafer fabricated in the ECE444 laboratory following boron predeposition, boron drive, and re-oxidation.

Repeat the process


At this point, the process of oxidation-photolithography-etching-diffusion can be repeated to produce the various types of electronic devices required for a circuit. Some modern processes may require more than 20 iterations of this sequence! Oxidation Photolithography Etching Diffusion (Ion Implantatio n) The following slides show the rest of the processes performed in the ECE444 lab.

ECE444 Process
Phosphorus Diffusion Photolithography Mask 2 Etch Phosphorus Predeposition

Gate Oxide Formation Photolithography Mask 3 Etch Gate oxidation

ECE444 Process
Electrical contact vias (holes) to silicon Photolithography Mask 4 Etch

Metal definition Photolithography Mask 5

Metallization
After all diffusion and oxidation steps are completed, metal is deposited onto the surface of the wafer. This metal is used to wire the devices fabricated in the silicon together. The wafers are put into a large chamber and the air is pumped out of the system. A piece of aluminum located on a tungsten boat in the system is heated to high temperature, causing the aluminum to melt and evaporate. The evaporated aluminum will solidify into a thin film when it touches the silicon wafer.

Thermal evaporation vacuum system used in the ECE444 laboratory. This tool was designed and built for an independent study project.

Metallization
After metallization, the wafer is completely covered by the aluminum. It must be patterned and etched to form the actual wires connecting individual devices into a circuit.

Wafer after aluminum evaporation

Completed wafer
Steps to create ECE444 wafer:

1. Initial oxidation 2. Photolithography Mask 1 3. Oxide etch 4. Boron predep 5. Boron drive and reoxidation 6. Photolithography Mask 2 7. Oxide etch 8. Phosphorus predeposition 9. Photolithography Mask 3 10. Gate oxidation 11. Photolithography Mask 4 12. Etch 13. Photolithography Mask 5 14. Metal evaporation 15. Metal definition

Time to see if it works

Testing
After completion of the wafer, it must be tested to verify operation. The devices fabricated are extremely small (some dimensions are as small a 1micrometer!), so specialized probes are used to make electrical contact. Once contact is made, several different instruments are used to measure electrical performance.

ECE444 Probe station

Example of electrical data from a device fabricated in the ECE444 laboratory

Silicon Manufacturing

HISTORY
19th Century - Solid-State Rectifiers 1907 - Application of Crystal Detector in Radio Sets 1947 - BJT Constructed by Bardeen and Brattain 1959 Integrated Circuit

Semiconductor Manufacturing Process

Semiconductor Manufacturing Process


Fundamental Processing Steps 1.Silicon Manufacturing

a) Czochralski method. b) Wafer Manufacturing c) Crystal structure


2.Photolithography

a) Photoresists b) Photomask and Reticles c) Patterning

Semiconductor Manufacturing Process (cont)


3.Oxide Growth & Removal

a) Oxide Growth & Deposition b) Oxide Removal c) Other effects d) Local Oxidation
4. Diffusion & Ion Implantation

a) Diffusion b) Other effects c) Ion Implantation

Silicon Manufacturing Crystal Growth and Wafer


Manufacturing

FABRICATING SILICON

Quartz, or Silica, Consists of Silicon Dioxide Sand Contains Many Tiny Grains of Quartz Silicon Can be Artificially Produced by Combining Silica and Carbon in Electric Furnice Gives Polycrystalline Silicon (multitude of crystals)

CRYSTAL GROWTH
Czochralski Process is a Technique in Making Single-Crystal Silicon A Solid Seed Crystal is Rotated and Slowly Extracted from a Pool of Molten Si Requires Careful Control to Give Crystals Desired Purity and Dimensions

CYLINDER OF MONOCRYSTALLINE
The Silicon Cylinder is Known as an Ingot Typical Ingot is About 1 or 2 Meters in Length Can be Sliced into Hundreds of Smaller Circular Pieces Called Wafers Each Wafer Yields Hundreds or Thousands of Integrated Circuits

WAFER MANUFACTURING
The Silicon Crystal is Sliced by Using a Diamond-Tipped Saw into Thin Wafers Sorted by Thickness Damaged Wafers Removed During Lapping Etch Wafers in Chemical to Remove any Remaining Crystal Damage Polishing Smoothes Uneven Surface Left by Sawing Process

THE CRYSTAL STRUCTURE OF SILICON


A Unit Cell Has 18 Silicons Atoms Weak Bonding Along Cleavage Planes Wafer Splits into 4 or 6 Wedge-Shaped Fragments Miller Indices is Used to Assign to Each Possible Plane Passing Through the Crystal Lattice

Silicon Manufacturing Photolithography

Photolithography
Photolithography is a technique that is used to define the shape of micro-machined structures on a wafer.

Photolithography Photoresist
The first step in the photolithography process is to develop a mask, which will be typically be a chromium pattern on a glass plate. Next, the wafer is then coated with a polymer which is sensitive to ultraviolet light called a photoresist. Afterward, the photoresist is then developed which transfers the pattern on the mask to the photoresist layer.

Photolithography Photoresist
There are two basic types of Photoresists Positive and Negative.
Positive resists.

Positive resists decomposes ultraviolet light. The resist is exposed with UV light wherever the underlying material is to be removed. In these resists, exposure to the UV light changes the chemical structure of the resist so that it becomes more soluble in the developer. The exposed resist is then washed away by the developer solution, leaving windows of the bare underlying material. The mask, therefore, contains an exact copy of the pattern which is to remain on the wafer.

Photolithography Photoresist
Negative resists

Exposure to the UV light causes the negative resist to become polymerized, and more difficult to dissolve. Therefore, the negative resist remains on the surface wherever it is exposed, and the developer solution removes only the unexposed portions. Masks used for negative photoresists, therefore, contain the inverse (or photographic "negative") of the pattern to be transferred.

Photolithography Model
Figure 1a shows a thin film of some material (eg, silicon dioxide) on a substrate of some other material (eg, a silicon wafer). Photoresist layer (Figure 1b )

Ultraviolet light is then shone through the mask onto the photoresist (figure 1c).

Photolithography Model (cont)


The photoresist is then developed which transfers the pattern on the mask to the photoresist layer (figure 1d).

A chemical (or some other method) is then used to remove the oxide where it is exposed through the openings in the resist (figure 1e).
Finally the resist is removed leaving the patterned oxide (figure 1f).

Photolithography Photomasks and Reticles


Photomask This is a square glass plate with a patterned emulsion of metal film on one side. The mask is aligned with the wafer, so that the pattern can be transferred onto the wafer surface. Each mask after the first one must be aligned to the previous pattern.

Photolithography Photomasks and Reticles


When a image on the photomask is projected several time side by side onto the wafer, this is known as stepping and the photomask is called a reticle.

An common reticle is the 5X

The patterns on the 5X reticle are reduced 5 times when projected onto the wafer. This means the dies on the photomask are 5 times larger than they are on the final product. There are other kinds of reduction reticles (2X, 4X, and 10X), but the 5X is the most commonly used. Reduction reticles are used on a variety of steppers, the most common being ASM, Canon, Nikon, and GCA.

Photolithography Photomasks and Reticles


Examples of 5X Reticles:

Photolithography Photomasks and Reticles


Once the mask has been accurately aligned with the pattern on the wafer's surface, the photoresist is exposed through the pattern on the mask with a high intensity ultraviolet light. There are three primary exposure methods: contact, proximity, and projection.

Photolithography Patterning
The last stage of Photolithography is a process called ashing. This process has the exposed wafers sprayed with a mixture of organic solvents that dissolves portions of the photoresist . Conventional methods of ashing require an oxygen-plasma ash, often in combination with halogen gases, to penetrate the crust and remove the photoresist. Usually, the plasma ashing process also requires a follow-up cleaning with wet-chemicals and acids to remove the residues and nonvolatile contaminants that remain after ashing. Despite this treatment, it is not unusual to repeat the "ash plus wet-clean" cycle in order to completely remove all photoresist and residues.

Silicon Manufacturing Oxidation of Silicon

SiO2 growth is a key process step in manufacturing all Si devices - Thick ( 1m) oxides are used for field oxides (isolate devices from one another ) - Thin gate oxides (100 ) control MOS devices - Sacrificial layers are grown and removed to clean up surfaces The stability and ease of formation of SiO2 was one of the reasons that Si replaced Ge as the semiconductor of choice.

The simplest method of producing an oxide layer consists of heating a silicon wafer in an oxidizing atmosphere.

Dry oxide - Pure dry oxygen is employed


Disadvantage - Dry oxide grows very slowly. Advantage - Oxide layers are very uniform. - Relatively few defects exist at the oxide-silicon interface (These defects interfere with the proper operation of semiconductor devices) - It has especially low surface state charges and thus make ideal dielectrics for MOS transistors.

Wet oxide - In the same way as dry oxides, but


steam is injected Disadvantage - Hydrogen atoms liberated by the decomposition of the water molecules produce imperfections that may degrade the oxide quality. Advantage - Wet oxide grows fast. - Useful to grow a thick layer of field oxide

Deposited Oxides
Oxide is frequently employed as an insulator between two layers of metalization. In such cases, some form of deposited oxide must be used rather than the grown oxides. Deposited oxides can be produced by various reactions between gaseous silicon compounds and gaseous oxidizers. Deposited oxides tend to possess low densities and large numbers of defect sites. Not suitable for use as gate dielectrics for MOS transistors but still acceptable for use as insulating layers between multiple conductor layers, or as protective overcoats.

Key Variables in Oxidation


Temperature
- reaction rate - solid state diffusion

Oxidizing species
- wet oxidation is much faster than dry oxidation

Surface cleanliness
- metallic contamination can catalyze reaction - quality of oxide grown (interface states)

Etching
Etching is the process where unwanted areas of films are removed by either dissolving them in a wet chemical solution (Wet Etching) or by reacting them with gases in a plasma to form volatile products (Dry Etching). Resist protects areas which are to remain. In some cases a hard mask, usually patterned layers of SiO2 or Si3N4, are used when the etch selectivity to photoresist is low or the etching environment causes resist to delaminate.

Wet Chemical Etching


Wet etches:
- are in general isotropic (not used to etch features less than 3 m) - achieve high selectivities for most film combinations - capable of high throughputs - use comparably cheap equipment - can have resist adhesion problems - can etch just about anything

Example Wet Processes


For SiO2 etching - HF + NH4F+H20 (buffered oxide etch or BOE) For Si3N4 - Hot phosphoric acid: H3PO4 at 180 C - need to use oxide hard mask Silicon - Nitric, HF, acetic acids - HNO3 + HF + CH3COOH + H2O Aluminum - Acetic, nitric, phosphoric acids at 35-45 C - CH3COOH+HNO3+H3PO4

What is a plasma (glow discharge)?


A plasma is a partially ionized gas made up of equal parts positively and negatively charged particles. Plasmas are generated by flowing gases through an electric or magnetic field. These fields remove electrons from some of the gas molecules. The liberated electrons are accelerated, or energized, by the fields. The energetic electrons slam into other gas molecules, liberating more electrons, which are accelerated and liberate more electrons from gas molecules, thus sustaining the plasma.

Dry or Plasma Etching

Dry or Plasma Etching

Dry or Plasma Etching


Combination of chemical and physical etching Reactive Ion Etching (RIE)
Directional etching due to ion assistance. In RIE processes the wafers sit on the powered electrode. This placement sets up a negative bias on the wafer which accelerates positively charge ions toward the surface. These ions enhance the chemical etching mechanisms and allow anisotropic etching. Wet etches are simpler, but dry etches provide better line width control since it is anisotropic.

Other Effects of Oxide Growth and Removal


Oxide Step - The differences in oxide thickness and in the depths of the silicon surfaces combine to produce a characteristic surface discontinuity The growth of a thermal oxide affects the doping levels in the underlying silicon The doping of silicon affects the rate of oxide growth

Local Oxidation of Silicon (LOCOS)


LOCOS: localized oxidation of silicon using silicon nitride as a mask against thermal oxidation. A technique called local oxidation of silicon (LOCOS) allows the selective growth thick oxide layers CMOS and BiCMOS processes employ LOCOS to grow a thick field oxide over electrically inactive regions of the wafer

Silicon Manufacturing Diffusion and Ion


Implantation

WN-Junction Fabrication (Earliest method)


Process:
Opposite polarity doping atoms are added to molten silicon during the Czochralski process to create in-grown junctions in the ingot. Repeated counterdopings can produce multiple junctions within the crystal.

Disadvantages
Inability to produce differently doped areas in different parts of the wafer. The thickness and planarity of grown junctions are difficult to control. Repeated counterdopings degrade the electrical properties of the silicon.

The Planar Process


Advantages:
The planar process does not require multiple counterdopings of the silicon ingot. This process allows more precise control of junction depths and dopant distributions.

Methods of planar process


Diffusion
A uniformly doped ingot is sliced into wafers. An oxide film is then grown on the wafers. The film is patterned and etched using photolithography exposing specific sections of the silicon. The wafers are then spun with an opposite polarity doping source adhering only to the exposed areas. The wafers are then heated in a furnace (800-1250 deg.C) to drive the doping

Ion Implantation
A particle accelerator is used to accelerate a doping atom so that it can penetrate a silicon crystal to a depth of several microns
Lattice damage to the crystal is then repaired by heating the wafer at a moderate temperature for a few minutes. This process is called annealing.

Diffusion Process Implantation

Ion

Comparison of Diffusion and Ion Implantation


Diffusion is a cheaper and more simplistic method, but can only be performed from the surface of the wafers. Dopants also diffuse unevenly, and interact with each other altering the diffusion rate. Ion implantation is more expensive and complex. It does not require high temperatures and also allows for greater control of dopant concentration and profile. It is an anisotropic process and therefore does not spread the dopant implant as much as diffusion. This aids in the manufacture of self-aligned structures which greatly improve the performance of MOS transistors.

References
The Art of Analog Layout by Alan Hastings 2001 Prentice-Hall
Semiconductor Devices by Mauro Zambuto 1989 McGraw-Hill Semiconductor Manufacturing Technology by Quirk and Serda 2001 Prentice-Hall

Introduction to the Semiconductor Industry

Objectives this chapter, you will be able to: After studying the material in
1. Describe the current economic state and the technical roots of the semiconductor industry. 2. Explain what is an integrated circuit (IC) and list the five circuit integration eras. 3. Describe a wafer, including how it is layered and describe the essential aspects of the five stages of wafer fabrication. 4. State and discuss the three major trends associated with improvement in wafer fabrication. 5. Explain what is a critical dimension (CD) and how Moores law predicts future wafer fabrication improvement. 6. Describe the different eras of electronics since the invention of the transistor up to modern wafer fabrication. 7. Discuss different career paths in the semiconductor industry.

Microprocessor Chips

Photo courtesy of Advanced Micro Devices

Photo courtesy of Intel Corporation


Photo 1.1

Development of an Industry Roots Industry


Vacuum Tubes Radio Communications Mechanical Tabulators Inventors Disadvantages

The Solid State


Solid State Physics The First Transistor Benefits

Vacuum Tubes

Photo 1.2

The Semiconductor Industry


INFRASTRUCTURE Industry Standards (SIA, SEMI, NIST, etc.) PRODUCT APPLICATIONS Consumers: Computers Automotive Aerospace Medical other industries Customer Service Original Equipment Manufacturers Printed Circuit Board Industry

Production Tools
Utilities Materials & Chemicals Metrology Tools

Chip Manufacturer

Analytical Laboratories
Technical Workforce Colleges & Universities

Figure 1.1

The First Transistor from Bell Labs

Photo courtesy of Lucent Technologies Bell Labs Innovations Photo 1.3

The First Planar Transistor

Figure 1.2

Circuit Integration
Integrated Circuits (IC)
Microchips, chips Inventors Benefits of ICs

Integration Eras
From SSI to ULSI 1960 - 2000

Jack Kilbys First Integrated Circuit

Photo courtesy of Texas Instruments, Inc.


Photo 1.4

Top View of Wafer with Chips


A single integrated circuit, also known as a die, chip, and microchip

Figure 1.3

Circuit Integration of Semiconductors


Circuit Integration No integration (discrete components) Small scale integration (SSI) Medium scale integration (MSI) Large scale integration (LSI) Very large scale integration (VLSI) Ultra large scale integration (ULSI) Semiconductor Industry Time Period Prior to 1960 Early 1960s 1960s to Early 1970s Early 1970s to Late 1970s Late 1970s to Late 1980s 1990s to present Number of Components per Chip 1 2 to 50 50 to 5,000 5,000 to 100,000 100,000 to 1,000,000 > 1,000,000

Table 1.1

ULSI Chip

Photo courtesy of Intel Corporation, Pentium III


Photo 1.5

IC Fabrication
Silicon
Wafer Wafer Sizes Devices and Layers

Wafer Fab Stages of IC Fabrication


Wafer preparation Wafer fabrication Wafer test/sort Assembly and packaging Final test

Evolution of Wafer Size


2000

1992 1987
1981
1975

1965

50 mm

100 mm

125 mm

150 mm 200 mm

300 mm

Figure 1.4

Devices and Layers from a Silicon Chip


Top protective layer

Conductive layer

Metal layer
Insulation layers

drain

Recessed conductive layer

Silicon substrate

Silicon substrate
Figure 1.5

Stages of IC Fabrication
Single crystal silicon 1.

Wafer Preparation includes crystal growing, rounding, slicing and polishing.

4. Assembly and Packaging:

Wafers sliced from ingot

The wafer is cut along scribe lines to separate each die.

Scribe line A single die Assembly Packaging

2.

Wafer Fabrication includes cleaning, layering, patterning, etching and doping.

Metal connections are made and the chip is encapsulated.

3.

Test/Sort includes probing, testing and sorting of each die on the wafer.

Defective die

5. Final Test ensures IC

passes electrical and environmental testing.

Figure 1.6

1. Crystal Growth

Preparation of Silicon Wafers


Polysilicon Seed crystal Crucible

6. Edge Rounding

Heater

7. Lapping 2. Single Crystal Ingot

8. Wafer Etching 3. Crystal Trimming and Diameter Grind


Slurry Polishing head

9. Polishong 4. Flat Grinding


Polishing table

5. Wafer Slicing

10. Wafer Inspection

(Note: Terms in Figure 1.7 are explained in Chapter 4.)


Figure 1.7

Wafer Fab

Photo courtesy of Advanced Micro Devices-Dresden, S. Doering


Photo 1.6

Sample of Microchip Packaging

Figure 1.8

Semiconductor Trends
Increase in Chip Performance
Critical Dimension (CD) Components per Chip Moores Law Power Consumption

Increase in Chip Reliability Reduction in Chip Price

Critical Dimension
Common IC Features
Line Width Contact Hole Space

Figure 1.9

Past and Future Technology Nodes for Device Critical Dimension (CD)
1988 CD (m) 1.0 1992 0.5 1995 0.35 1997 0.25 1999 0.18 2001 0.15 2002 0.13 2005 0.10

Table 1.2

Microprocessor Total Transistors in Millions

Increase in Total Transistors/Chip


1600 1400 1200 1000 800 600 400 200

1997 1999 2001 2003 2006 2009 2012 Year Redrawn from Semiconductor Industry Association, The National Technology Roadmap for Semiconductors, 1997. Figure 1.10

100M

Moores Law for The number of transistors on a chip double every 18 months. Microprocessors
500
Pentium

10M
Pentium Pro

1M
80386

80486

25

100K
8086

80286

1.0

10K
8080 4004

.1

1975

1980

1985 Year

1990

1995

.01 2000

Used with permission from Proceedings of the IEEE, January, 1998, 1998 IEEE Figure 1.11

Size Comparison of Early and Modern Semiconductors


1990s Microchip (5~25 million transistors) 1960s Transistor

U.S. coin, 10 cents

Figure 1.12

Reduction in Chip Power Consumption per IC


10 Average Power in micro Watts (10-6 W) 8

0 1997 1999 2001 2003 Year Redrawn from Semiconductor Industry Association, National Technology Roadmap, 1997
Figure 1.13

2006

2009

2012

Reliability Improvement of Chips


700 600

Long-Term Failure Rate Goals in parts per million (PPM)

500 400

300

200 100 0 1972

1976

1980

1984

1988

1992

1996

2000

Year
Figure 1.14

Price Decrease of Semiconductor Chips


104 102 1 Relative value 10-2 10-4 10-6
ULSI Electron tubes Standard tube Miniature tube Semiconductor devices Bipolar transistor Integrated circuits MSI LSI VLSI

Device size = Price =

10-8

10-10 1930

1940

1950

1960 1970 Year

1980

1990

2000

Redrawn from C. Chang & S. Sze, McGraw-Hill, ULSI Technology, (New York: McGraw-Hill, 1996), xxiii. Figure 1.15

The Electronic Era


1950s: Transistor Technology 1960s: Process Technology 1970s: Competition 1980s: Automation 1990s: Volume Production

Start-Up Cost of Wafer Fabs


$100,000,000,00 0 Actual Costs Projected Costs $10,000,000,000 Cost

$1,000,000,000

$100,000,000

1970 $10,000,000

1980

1990

2000 Year

2010

2020

Used with permission from Proceedings of IEEE, January, 1998 1998 IEEE
Figure 1.16

Career Paths in the Semiconductor Industry


Fab Manager Maintenance Manager Production Manager Engineering Manager MS

Maintenance Supervisor

Production Supervisor

Process Engineer

BS

Equipment Engineer

Associate Engineer

BSET*

Equipment Technician

Yield & Failure Analysis Technician

AS+

Maintenance Technician Manufacturing Technician

Process Technician

Lab Technician

AS HS +

Wafer Fab Technician

Production Operator

* Bachelor of Science in Electronics Technology

HS Educatio n

Figure 1.17

Productivity Measurements in a Wafer Fab


Misprocessing
Photo Production Bay
12

Ion Implant Production Bay Scrap

Diffusion Production Bay Productio n Equipmen t

Rework
9 6 3

Production Equipment

Cycle Time per Operation


Time In

Inspectio n

Production Equipment

Inspectio n

Inspectio n

Time Out

Wafer Starts
1 2 3 4 6 7 8 9 10 11

Wafer Moves

Wafer Outs
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

12 13 14 15 16 17 18

19 20 21 22 23 24 25

26 27 28 29 30 31

Production Equipment

Inspectio n

Production Equipment

Inspectio n

Production Equipment

Inspectio n

30 31

Etch Production Bay

Thin Films Production Bay

Metallization Production Bay

Production Cycle Time = (Date and Time of Wafer Start) - (Date and Time of Wafer Out) Wafer Outs = Wafer Starts - Wafers Scrapped Operator Efficiency = Theoretical Cycle Time / Actual Cycle Time

Figure 1.18

Equipment Technician in a Wafer Fab

Photograph courtesy of Advanced Micro Devices


Photo 1.7

Technician in Wafer Fab

Photo courtesy of Advanced Micro Devices


Photo 1.8

IC Fabrication An Introduction

Integrated circuit showing memory blocks, logic and input/output pads around the periphery

Six Level of Interconnection

IC device
drain

Silicon chip

High lead solder die attach

Tin/lead plated copper leadframe

Semiconductor Applications
3C : Computer--- /Communication / Consumables

Personal Computer--- Desktop Computer (DT) /


Notebook (NB)

Communication--ADSL / Cable Modem / IEEE802.11X / Bluetooth / VoIP

Consumables--Game / DVD / Digital Camera

3C merge--- Digital Home

Types of Chips
Dynamic Random Access Memory chips (DRAMs) - serve as the primary memory for
computers

Microprocessors (MPUs) - act as the brains of


computers.

Application Specific Integrated Circuits (ASICs)

- are custom semiconductors designed for very specific


functions

Digital Signal Processors (DSPs) - process signals,


such as image and sound signals or radar pulses.

Programmable memory chips (EPROMs, EEPROMs, and Flash) - are used to perform

functions that require programming on the chip.

Semiconductor Fabrication Processes


Front-End Processing (Wafer fabrication) Back-End Processing (Assembly and Testing)

Logic Circuit Design / Layout Design


A logic circuit diagram is drawn to determine the electronic circuit required for the requested function. Once the logic circuit diagram is complete, simulations are performed multiple times to test the circuits operation.

Photomask Creation
The photomask is a copy of the circuit pattern, drawn on a glass plate coated with a metallic film. The glass plate lets light pass, but the metallic film does not. Due to increasingly high integration and miniaturization of the pattern, the size of the photomask is usually magnified four to ten times the actual size.

The photomask of a RF IC Chip

Wafer Fabrication
A high-purity, single-crystal silicon called "99.999999999% (eleven-nine)" is grown from a seed to an ingot. The wafers are generally available in diameters of 150 mm, 200 mm, or 300 mm, and are mirrorpolished and rinsed before shipment from the wafer manufacturer.

Deposition
the wafer is placed in a high-temperature furnace to make the silicon react with oxygen or water vapor, and to develop oxide films on the wafer surface (thermal oxidation). To develop nitride films and polysilicon films, the chemical vapor deposition (CVD) method is used, in which a gaseous reactant is introduced to the silicon substrate, and chemical reaction produce the deposited layer material. The metallic layers used in the wiring of the circuit are also formed by CVD, spattering (PVD: physical vapor deposition)

Photoresist Coating
A resin called "photoresist" is coated over the entire wafer. (~1m thick coating.) Photoresist is a special resin similar in behavior to photography films that changes properties when exposed to light.

Masking/Exposure
Placed over the photoresist-coated wafer, which is then irradiated to have the circuit diagram transcribed onto it. An irradiation device called the "stepper" is used to irradiate the wafer through the mask with ultraviolet (UV) light.

Lithography area in clean room

Patterning: Development
The photoresist chemically reacts and dissolves in the developing solution, only on the parts that were not masked during exposure (positive method). Development is performed with an alkaline developing solution. After the development, photoresist is left on the wafer surface in the shape of the mask pattern.

Etching
"Etching" refers to the physical or chemical etching of oxide films and metallic films using the resist pattern as a mask. Etching with liquid chemicals is called "wet etching" and etching with gas is called "dry etching".

Photoresist Stripping
The photoresist remaining on the wafer surface is no longer necessary after etching is complete. Ashing by oxygen plasma or the likes is performed to remove the residual photoresist.

Device Insulation Layer (FieldOxide Film) Formation


After the oxide film and nitride film are developed, a resist pattern is formed on the regions that will become the device insulation layer. Ion implantation is performed on the wafer, forming a p-type diffusion layer. Next, the oxide film and nitride film on the diffusion layer are etched. Using the nitride film pattern as the mask, the oxide film that will become the device insulation layer is developed.

Transistor Formation
A transistor is a semiconductor device with a switching function and three terminals: source, drain, and gate. An insulation layer called "gate oxide" is first formed on the wafer surface. A polysilicon film is deposited onto the gate oxide, and a polysilicon gate for controlling the flow of electrons between the source region and the drain region is formed by lithography and etching. After the polysilicon gate is formed, an ntype diffusion layer consisting of both the source and the drain regions is formed by implantation of impurities

Polysilicon Gate Cross-Section Image

Metallization
Interconnecting the devices, such as transistors, formed on the silicon wafer completes the circuit. the wafer is first covered with a thick and flat interlayer insulation film (oxide film). Next, contact holes are drilled by lithograph and etching, through the interlayer insulation film, above the devices to be connected.

Nine-layer Copper Interconnect Architecture

Wafer Inspection
Each IC on the completed wafer is electronically tested by the tester. After this inspection, the front-end processing is complete.

Dicing
In back end processing, a wafer completed in front end processing is cut into individual IC chips and encapsulated into packages.

Mounting
After the IC chips are cut apart, they are sealed into packages. The IC chips must first be attached to a platform called the "lead frame.

Wire bonding
The mounted IC chips are connected to the lead frames.

Encapsulation
The IC chips and the lead frame islands are encapsulated with molding resin for protection.

Characteristic Selection
The packaged IC chips are tested and selected.

Printing and Lead Finish


The final step of IC chip manufacturing is the printing onto the package surface and the finishing of leads. After this step, the IC chips are complete.

You might also like