9309 - CMOS Analog Design Chapter 8

CMOS Analog Design Using All-Region MOSFET
Modeling
1

CMOS Analog Design Using
All-Region MOSFET Modeling

Chapter 8
Operational amplifiers
Modeling
2
+

v
i

-
+

-
G
m
v
i
G
S

+
v
o
-
G
m
=AG
S
+

v
i

-
+

-
+
Av
i
-
R
S

+
v
o
-
A
R
S
=0
+
-
The ideal operational amplifier
Modeling
3
2 2
1 1
2
1
1
1 1
1
1 1
o
i
v R R
v R R
R
A R
| |
= + ~ +
|
| |
\ .
+ +
|
\ .
+
v
i
-
-

+
R
2

R
1

+
v
o
-
Inverting amplifier
2 2
1 1
2
1
1
1
1 1
o
i
v R R
v R R
R
A R
= ~
| |
+ +
|
\ .
-

+
R
2

R
1

+
v
i
-
+
v
o
-
Non inverting amplifier
Applications of operational amplifiers - 1
Modeling
4
Transimpedance amplifier
2 2 2
1
1
1
o
v A
R R R
i A A
| |
= ~ ~
|
+
\ .
-

+
R
2

i
+
v
o
-
- Continuous-time filters
- SC filters
- D/A & A/D converters
- Sensor signal conditioning
- Voltage & current references
- Comparators
- Nonlinear analog functions,
- .......
(d)
C
+
v
o

-
-

+
R
+
v
i
-
Modeling
5
C
+
v
o

-
-

+
R
+
v
i
-
R
|
1

|
2

C
2

+
v
o

-
-

+
+
v
i
-
C
1

|
1

|
2
|
2

|
1

S/H circuit
Switched-capacitor
integrator
Modeling
6
Performance parameters of op amps - 1
Table 8.1 Measured dc and ac characteristics
of the buffered op amp of reference [7].
10 mW Power dissipation
0.88 V Vout-
4.12 V Vout+
1 mV Offset voltage
18.8 V/s SR
-
(50 O|| 33 pF load)
20.4 V/s SR
+
(50 O|| 33 pF load)
11.4 MHz Gain-bandwidth product
67.2 dB DC gain (163O|| 33 pF load)
5 V Supply voltage
Modeling
7
Performance parameters of op amps - 2
Table 8.2 Experimental performance of the operational amplifiers
of [8] (V
supply
= 1 V, Technology: 1.2-m CMOS, C = 15 pF).
56.7 dB
51.5 dB
54.4 dB
52.1 dB
PSRR
+

PSRR
-

58 dB 62 dB CMRR
359 nV/\Hz
171 nV/\Hz
82 nV/\Hz
267 nV/\Hz
91 nV/\Hz
74 nV/\Hz
v
ni
(@ 1 kHz)
v
ni
(@ 10 kHz)
v
ni
(@ 1 MHz)
-77 dB
-57 dB
-54 dB
-32 dB
THD (0.5 V
pp
@ 1 kHz)
THD (0.5 V
pp
@ 40 kHz)
0.9 V/s
1.7 V/s
0.8 V/s
1 V/s
SR
+

SR
-

73
o
61
o
Phase margin
2.1 MHz 1.9 MHz Unity-gain frequency
70.5 dB 87 dB DC gain
208 A 410 A I
DD
(supply current)
0.26 mm
2
0.81 mm
2
Active die area
Amplifier II Amplifier I Parameter
Modeling
8
C
L

I
2

I
T

I
1
= I
3
i
0
M
4
M
3

I
4
v
O

+
v
G1

-
M
1

M
2

+
v
G2

-
+ -
1:1
V
SS

Low gain
Reduced output swing
What is the maximum output swing
when the conventional differential pair is
used for a buffer?
The differential amplifier as an op amp - 1
Modeling
9
What is the maximum output swing
when the telescopic-cascode
differential pair is used for a buffer?
V
O

M
7

M
6

+
V
G1
-
V
DD

+
V
G2
-
M
5

I
T

M
1

M
2

V
X

M
3

M
4

M
8

V
BN

V
BP

Telescopic-cascode differential amplifier
The differential amplifier as an op amp - 2
Modeling
10
The symmetric op amp - 1
V
SS

I
T

+
v
G1

-
M
1

M
2

I
1
I
2

+
v
G2

-
Current
Mirror
B:1
C
L
BI
1
BI
2

BI
1

I
o
= B(I
2
-I
1
)
Current
Mirror
1:B
1:1
Current
Mirror
Modeling
11
V
O
M
1
M
2

+
V
G1
-
+
V
G2
-
M
4

1:B
I
T

V
X

M
3

M
5

V
DD

M
6

M
7
M
8

B:1
1:1
C
L

I
L

V
Y

-1
I
1
/I
T

I
2
/I
T

0 4 2 -2 -4
1
I
L
/BI
T

V
ID
(a.
u.)
Modeling
12
Common-mode input range:
see diff. amp.
( )
T
L P
BI
SR
C C
=
+
( )
( )
1
1
m o
d
o L P
Bg R
A s
sR C C
=
+ +
( )
1
1
(Hz)
2
m
L P
Bg
GB
C C t
=
+
Current mirrors delays were
neglected
I
o
= B(I
2
-I
1
)
V
SS

I
T

+
v
G1

-
M
1
M
2

I
1
I
2

+
v
G2

-
B:1 1:B
1:1
BI
1
BI
2

BI
1

C
L
asymmetry
1 2 id g g
v v v =
C
L
+C
P
1 m id
Bg v
o
R
+
v
o
-

Modeling
13
Telescopic differential amplifier with
high-swing cascode current mirror
Suppose that the high-swing telescopic
op amp will be used in an application
such that V
ICM
is constant and chosen
as equal to the minimum voltage such
that I
SS
remains in saturation. In this
case, what would be the maximum
output swing when V
b1
and V
b2
are
optimally biased?
V
O

M
7

M
6

+
V
G1
-
V
DD

+
V
G2
-
M
5

I
T

M
1

M
2

V
X

M
3
M
4

M
8

V
BN

V
BP

Problem:
Modeling
14
Folded cascode amplifiers - 1
I
T

I
T
/2 I
T
/2
Ai
Ai
2Ai
M
1

M
2

M
3
M
4

M
5

M
6

M
7
M
8

M
9
M
10

M
11

+ -
I
B

I
B

Ai
Ai
Ai
V
DD

V
SS

V
bias2

+
v
o

-
C
L

v
i1

v
i2

V
bias1

N2 N1
V
bias3

Can be replaced with
high-swing current
mirror to increase
positive output swing
Modeling
15
I
T

i
o

M
1
M
2

M
3
M
4

M
5
M
6

M
7
M
8

M
9
M
10

M
11

+ -
I
T

I
T

V
DD

V
SS

V
B3

+
v
o

-
C
L

v
i1

v
i2

V
B2

V
B1

V
B4

V
D
D

I
REF

M
16

M
12

V
SS

M
13

M
14

M
15

to
V
B
1

to
V
B2

to
V
B3

to
V
B4
M
17

M
18

Bias network
What is the maximum achievable
output swing?
The common-mode input range is
V
ICM,min
~V
SS
;
V
ICM,max
=V
DD
-V
DSsat11
-V
SG1
Modeling
16
( )
( )
1 2 01 02
1 2
1 1 2
5
5 6 05 06
1
5 6
1 5 6
9
9 10 09 010
1
9 10
1 9 10

2( / 2)

2

OS T T
S S T
m S S
m
OS T T
m
S S B T
m S S
m
OS T T
m
S S B
m S S
V V V
I I I
g I I
g
V V V
g
I I I I
g I I
g
V V V
g
I I I
g I I
= +
+
= +

+
=
+
I
T

i
o

M
1

M
2

M
3
M
4

M
5

M
6

M
7
M
8

M
9
M
10

M
11

+ -
I
T

I
T

V
DD

V
SS

V
B3

+
v
o

-
C
L

v
i1

v
i2

V
B2

V
B1

V
B4

Offset voltage
Modeling
17
0
0
1
d
d
L
A
A
sC R
~
+
Note: The output swing can be
around -V
SS
+2V
DSsatn
to V
DD
-
2V
SDsatp
for optimized bias.
R
o

T
L
I
SR
C
=
0 d m o
A G R =
& doublet
1 m m
G g =
( )
8
6
8
4
10 2
4
1
md
o ds
o ms
md
md md
ms
g
G g
R g
g
g g
g
= =
+ +
I
T

i
o

M
1

M
2

M
3
M
4

M
5
M
6

M
7
M
8

M
9
M
10

M
11

+ -
I
T

I
T

V
DD

V
SS

V
B3

+
v
o

-
C
L

v
i1

v
i2

V
B2

V
B1

V
B4

Modeling
18
1 2
(1 )
2
o d mir d
cm
icm icm
mi mi
t mir
t mi mi
i i i
G
v v
g g
y
y ng g
c
c

= = ~
| |
A
|
+
\ .
N-well of input transistors to V
DD

/ 1 2 /
/
o id mi t
mi
o icm
mir
mi
i v ng y
CMRR
g
i v
g
c
+
= ~
A
CMRR
I
T

i
o

M
1

M
2

M
3
M
4

M
5
M
6

M
7
M
8

M
9
M
10

M
11

+ -
I
T

I
T

V
DD

V
SS

V
B3

+
v
o

-
C
L

v
i1

v
i2

V
B2

V
B1

V
B4

Modeling
19
( )( ) ( )
1 9 2 10
1 2
10 9 9
1 2
1
2
d d mir d d o
vss
ss ss
ms ms ss
ss ds ds mir ds
ms ms
i i i i i
G
v v
g g g
g g g g
g g
c
c
+ +
= =
| |
~ + + +
|
+
\ .
1
1 2 10 9 9
1 2 1 1 1 1
1

2
vss
vss m
ms ms ss ds ds ss ds
mir
ms ms m m m m
G
PSRR g
g g g g g g g
g g g g g g
c
=
| |
= + + +
|
+
\ .
PSRR
vss

I
T

i
o

M
1

M
2

M
3
M
4

M
5
M
6

M
7
M
8

M
9
M
10

M
11

+ -
I
T

I
T

V
DD

V
SS

V
B3

+
v
o

-
C
L

v
i1

v
i2

V
B2

V
B1

V
B4

Modeling
20
Noise
2 2 2 2
1 5 9
2
no n n n
i i i i
f f
| |
+ +
~ |
|
A A
\ .
Input-referred noise
2 2 2 2
1 5 9
2
1
2
ni n n n
m
e i i i
f g f
| |
+ +
~ |
|
A A
\ .
I
T

i
o

M
1

M
2

M
3
M
4

M
5
M
6

M
7
M
8

M
9
M
10

M
11

+ -
I
T

I
T

V
DD

V
SS

V
B3

+
v
o

-
C
L

v
i1

v
i2

V
B2

V
B1

V
B4

Modeling
21
Output swing:
6 7 DD DSsat o SS DSsat
V V V V V > > +
For systematic offset 0.
V
DD

C
L
V
SS

M
4
M
3

M
1
M
2

M
8

M
5

M
7

M
6

I
T

v
i
+

-

C
C
v
o
1:1

1:B

1:1

1:2B

inv
non inv

1:2B
( )
6 4 7 5
/ 2 / S S S S =
0
0
2

2
SN T
OS T N
mn SN
mp
SP T
T P
mn mn SP
I I
V V
g I
g
I I
V
g g I
A
= A +
A
A +
~ same offset voltage as diff. amp.
Two-stage amplifiers - 1
Common-mode input range:
see diff. amp.
Modeling
22
v
oI

g
oI

+
v
id
-
g
mI

+

-
C
oI

v
o

g
oII

C
L

-g
mII

Frequency
compensation
i
oI

V
DD

C
L
V
SS

M
4
M
3

M
1
M
2

M
5

M
7

M
6

I
T

v
i
+

-

C
C
v
o
1:B

1:1

1:2B

inv
non inv

Modeling
23
Equivalent differential circuit
1 mI m
g g =
( )
1
2 4
2 4 6 6
I ds ds
I db db gb gs
R g g
C C C C C
= +
= + + +
6 mII m
g g =
( )
1
6 7
6 7
II ds ds
II db db L
R g g
C C C C
= +
= + +
For C
C
0
( )
( ) ( )
1 1
o mI mII I II
in I I II II
V g g R R
s
V sR C sR C
~
+ +
Poles relatively close phase margin
can be low or even negative !!!
Exercise: Derive the transfer function A
d
(s)
of the compensated operational amplifier
+
v
in

-
R
I

gm
I
v
in

C
I

+
v
I

-
gm
II
v
I

R
II

C
II

+
v
o

-
C
C
Modeling
24
v
oI

g
oI

+
v
id
-
g
mI

+

-
C
oI

v
o

g
oII

C
L

-g
mII

Frequency
compensation
i
oI

Frequency
compensation
C
C

( )( )
0
/
1 / 1 /
C
o mI mII oI oII
id oI oI L oII
C
V g g g g
V sC g sC g
=
=
+ +
C
C
=0
( ) ( )
( )
( )( )
0
1 2
1
1 / 1 /
d
o
d
id
A s z
V
A s s
V s p s p
= =

0 d mI mII I II
A g g R R =
( ) ( )
1
1 1
I I C II II C mII I II c mII I II c
p
R C C R C C g R R C g R R C
~ ~
+ + + +
( )
2
mII c
I II
mII
I I I C I I
g C
p
C C C C C
g
C
~ ~
+ +
mII
c
g
z
C
=
C
C
=0
Modeling
25
( ) ( )
( )
( )( )
0
1 2
1
1 / 1 /
d
o
d
in
A s z
V
A s s
V s p s p
= =

( ) ( )
1
1 1
p
~ ~
+ + + +
( )
2
mII c
I II
mII
I I I C I I
g C
p
C C C C C
g
C
~ ~
+ +
mII
c
g
z
C
=
s-plane
je
p
1

p
2

-g
oI
/C
oI
-g
oII
/C
L

z
o
Poles for C
C
=0
Poles for C
C
=0
Pole splitting
Modeling
26
When you design an op amp
you must take into account
both load and feedback loop.
|A
V
|
dB

g
oI
/C
oI

0
e
u
g
oII
/C
L

(a) Uncompensated op amp
| (rad)
0
-t/2
-t
e
u

g
oII
/C
L
g
oI
/C
oI

loge
|A
V
|
dB

z
0
e
u

-p
1

-p
2

loge
(b) Compensated op amp
| (rad)
0
-t/2
-t
e
u

z
-p
2

-p
1

PM
Modeling
27
( ) ( )
( )
( )( )
0
1 2
1
1 / 1 /
d
o
d
in
A s z
V
A s s
V s p s p
= =

( ) ( )
1
1 1
p
~ ~
+ + + +
( )
2
mII c
I II
mII
I I I C I I
g C
p
C C C C C
g
C
~ ~
+ +
mII
c
g
z
C
=
1 1 1 1
2
tan tan tan 1 tan
2 2
u u mI oI oI mI L
mII C C L mII
g C C g C
PM
p z g C C C g
e e t t

| |
| | | | | |
| |
= = + +
|
| | | |
|
\ .
\ . \ . \ .
\ .
1 1
tan 1 tan
2
u L oI oI u L C
mII C L mII L
C C C C C
PM
g C C g C
e e t

| |
| | | |
= + +
|
| |
|
\ . \ .
\ .
Modeling
28
CMRR: same as in differential amplifier
0 0
ssII ssI
o iII oI vssII ssII
v v
i A i Y v
= =
= + ( )
0
ssI
o iII mI id mvssI ssI mvssII ssII
v
i A Y v Y v Y v
=
= + +
1 1 1
mvssII oI
vss vssI iII mI vssI mI vssII
Y Y
PSRR PSRR A Y PSRR Y PSRR
= + = +
( )
mI mI mI
oI oI C oI oI C
Y g g
Y g s C C g sC
= ~
+ + +
7
mII mII
vssII
mvssII ss ds L
Y g
PSRR
Y Bg g sC
= ~
+ +
Modeling
29
Noise
v
oI

g
oI

g
mI

+

-
C
oI

v
o

g
oII

C
L

-g
mII

e
nII

e
nI

C
C

2 2 2
2
2 2
,
2
0
1
nII i
nII oI nII
mI u V I u
e
e g e
f f g f A
e e
e e
( (
| | | | | |
( ( = + = +
| | |
A A A
( (
\ . \ . \ .

Input-referred noise of the second stage
2
2
2 2 2 2
,
2
0
1
nII i
ni nI nI nII
V I u
e
e e e e
f f f f f A
e
e
(
| |
( = + = + +
|
A A A A A
(
\ .

Noise of 1
st
stage prevails over
that of the 2
nd
stage

except for
frequencies approaching e
u

Modeling
30
/
T C
SR I C
+
=
M
5

V
O

M
1
M
2

+
V
G1
-
V
DD

+
V
G2
-
I
T

C
L

M
3

M
4

I
L

1:1 1:2B
C
C

M
6

M
7

inv
ninv
V
OI

I
C

BI
T

I
D6

( )
1
min ,
T
T
L C
B I
I
SR
C C
| |
=
|
\ .
Modeling
31
0 0
max
; sin ;
o o
o
dv dv
SR v A t A SR
dt dt
e e s = = s
Amplitude x frequency limitation due to SR
J. Dostl, Operational Amplifiers, 2nd.
Ed., Butterworth-Heinemann, Boston,
1993.
Amplitude limitation
SR-limited slope
Modeling
32
Elimination of the feed forward
effect of C
C
using a buffer
C
L

M
5

V
O

M
1
M
2

V
DD

I
T

M
3

M
4

1:1
1:2B
C
C

M
6

M
7

BI
T

I
B

M
8

V
DD

+1
v
oI

g
oI

+
v
id
-
g
mI

+

-
C
oI

v
o

g
oII

C
L

-g
mII

i
oI

C
C

+1
Modeling
33
Nulling resistor
g
oII

v
oI

g
oI

+
v
id
-
g
mI

+

-
C
oI

v
o

C
L

-g
mII

i
oI

C
C

R
Z

M
5

V
O

M
1
M
2

V
DD

I
T

C
L

M
3

M
4

1:1 1:2B
C
C

M
6

M
7
BI
T

M
8

Bias

Modeling
34
No general rules
Specs depend on the application:
-
+
-
+
CMIR changes (diff. amp. with
complementary input pairs can
be required)
-
+
CMIR =0
Capacitive load
-
+
RC load
Some comments on op amp design - 1
Modeling
35
Scalable design:
-
+

C
-
+
m
mC
Switched circuits with f
sample
>>f
Nyquist
- SR is not important
but settling time is
Some comments on op amp design - 2
Improved SNR and
matching for m>1
Modeling
36
+
v
id
-
g
mI

+

-
g
mII

v
o

C
L

-g
mIII

C
mII

C
mI

-g
mfII

g
mfI

+

-
3-stage op amp with nested Miller compensation (NMC). The nested
transconductance-capacitance compensation (NGCC) amplifier is the
NMC + two transconductors (dashed lines).
Three-stage amplifiers
Modeling
37
I
T

M
1

M
2

M
9
M
10

M
11

+ -
V
SS

V
bias1

V
bias3

V
SDsat11

V
SG1

V
SD1

V
DS9
~V
DSsat9

Problem of the p-channel input
differential pair : V
ICM
<V
DD

Similarly, for the n-channel
input pair : V
ICM
>V
SS

How to get a rail-to-rail
differential amplifier ?
Combine p- and n-channel
input differential pairs
Rail-to-rail input stages - 1
Modeling
38
Transconductance, noise, and offset voltage are not constant over the
input range. The current switches block is included to keep the
transconductance approximately constant over the input range.
Combining p- and n-channel input differential pairs
I
T1

i
o
M
1
M
2

M
3

M
4

M
5

M
6

M
7

M
8

M
10

V
DD

V
SS

+v
in

-v
in

V
B2

V
B1

I
T2

I
B

I
B

M
9

Current
switches
V
SS

V
DD

Rail-to-rail input
differential amplifier
Rail-to-rail input stages - 2
Modeling
39
Class-A amplifiers: poor efficiency and high quiescent power
V
I

V
DD

V
SS

V
O

I
B

I
O

R
L

-R
L
I
B

V
O

V
DD
-V
DSsat

V
I

(a) CMOS class-A
source follower
(b) voltage transfer curve
0
1
1
O
V
I
m L
V
A
V
n
g R
= =
+
Class-AB output stages - 1
Modeling
40
V
O

V
DD
-V
Dssat1

V
I

V
SS
+|V
Dssat2
|
(b)
V
DD

V
I

V
SS

V
O

I
O

(a)
M
1

M
2

(a) CMOS class-B source follower
Modeling
41
(a)
V
DD

V
SS

V
O

I
O

V
I

I
B

M
1

M
2

M
4

M
3

1:N
1:N
V
O

V
DD
-V
DSsat1

V
I

V
SS
+|V
DSsat2
|
(b)
V
I0

(a) CMOS class-AB source follower
Problem for low-voltage supply: Output voltage cannot
swing close to the supply rails & stacked diodes
Modeling
42
CMOS common-source output stage and push (I
P
)
and pull (I
N
) currents versus output current.
Modeling
43
Rail-to-rail output stage and bias circuit for class-AB operation
Modeling
44
Two-stage op amp with rail-to-rail class-AB output stage
Modeling
45
R
2

+
v
od

-
-

+
R
1

+
v
id
-
R
1

+
-
R
2

v
o1

v
o2

t
t
t
t
v
od

V
ocm

V
ocm

FD = Fully-differential
SE = Single-ended
FD SE
V
opp
2: 1
Noise power 2: 1
SNR 2: 1
Even-order harm. No (match) Yes
CMRR, PSRR Improved
CMFB circuit Yes No
Area ~2: 1
Fully-differential amplifiers - 1
Modeling
46
M
1

M
2

M
6

M
3

M
4

+
-
V
DD

V
SS

V
bias

v
o2

v
i1

v
i2

v
o1

+ -
M
5

I
T
/2
I
T
/2
+
M
3r

I
T
/2
M
1r

M
5r

V
cm,ref

A
A
1

Example of idealized FD amplifier (transistors assumed to be matched) and
bias network employed to set the common-mode output voltage to V
cm,ref
.
Modeling
47
V
DD

I
T

M
1

M
2

M
5

M
3

M
4

+
-
V
SS

V
bias

v
o2

v
i1

v
i2

v
o1

+
V
cm,ref

R R
A
V
DD

I
T

M
1r

M
2r

M
5r

M
3r
M
4r

+
-
V
SS

V
bias

out
Simplified scheme of an FD amplifier. On the right is the low-gain
amplifier, a replica of the main amplifier but with diode connected loads.
Modeling
48
V
DD

I
T
/4
M
2
M
1

M
5

M
4
M
3

-
+
V
cm,ref

I
T

M
1
M
2

M
5

M
3
/2
+
-
v
o2

v
i1

v
i2

v
o1

R R
V
ocm
V
ocm

2M
3

M
5

I
T

V
SS

I
T
/4
I
T

C
L
C
L

M
3
/2
M
4
/2
M
4
/2
FD amplifier with resistive CM detector and the error amplifier on the
right employed to set the common-mode output voltage to V
cm,ref
.
Modeling
49
V
cm,ref

V
SS

I
T

4M
1

8M
1

2M
5

2I
T

4M
1
4M
1

M
5

M
3

+
-
v
o2

v
i1

v
i2

v
o1

V
ocm

M
3

M
5

I
T

I
T

I
T

M
3

4M
1

to
V
cm,ref
(or V
SS
)
R R
V
ocm

An FD amplifier where the two CM transconductors are
replicas of the DM transconductor
Modeling
50
M
1

v
i1

2M
1

V
DD

4M
1
4M
1

M
3

+
-
v
o2

v
i2

v
o1

I
T

M
3

V
SS

M
1

2M
1

V
cm,ref

M
1

v
o1

M
1

v
o2

2M
3

I
T
/2
I
T
/2
I
T
/2
I
T
/2
I
T
/4 I
T
/4
An FD amplifier employing CM detection based on differential
pairs which are replicas of the DM transconductor
Modeling
51
2M
4C

V
DD

I
T

M
1A
M
2A

M
5A

M
3A

M
4A

+
-
V
SS

v
o2

v
i1

v
i2

v
o1

V
cm,ref

M
5B

V
cm,ref

I
T
/2
I
T
/2
I
T

M
6A

M
7A
M
6B

M
7B

2M
4B

An FD amplifier using transistors in the triode region
to set the common-mode output voltage to Vcm,ref
Modeling
52
Complete schematic of an FD two-stage op amp
including the CM control circuit
Modeling
53
Complete schematic of an FD folded-cascode op
amp fabricated in 1.75 m CMOS technology
Modeling
54
I
T

A
4M
1

4M
2

M
3
M
4

M
5

M
6

M
7
M
8

M
9

M
10

M
11

+ -
I
T

I
T

V
DD

V
SS

V
B3

v
o1

v
i1

v
i2

V
B2

V
B1

V
B4

v
o2

B
+
-
(a)
I
T
/2
I
T
/2
M
1

2M
2

M
12

M
12

V
SS

M
1

2M
2

V
cm,ref

M
1

v
o1

M
1

v
o2

2M
12

I
T
/2
I
T
/2
I
T
/2
I
T
/4 I
T
/4
(b)
A
B
i
oA

i
oB

Simplified schematics of (a) folded-cascode op amp
and (b) common-mode feedback circuit

9309 - CMOS Analog Design Chapter 8

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