Embedded System architecture

Differences between RISC AND CISC Architecture

RISC
1)Simple instruction set 2) Requires single cycle 3) Very few instructions refer memory 4) Instruction are executed by hardware 5) Fixed instruction Form at 6) Few addressing modes 7) Does not support complex addressing modes 8)Multiple register set 9) Highly pipelined

CISC
1) Complex instruction set 2) Requires multiple cycle 3) Many instruction refer memory
4) Instructions are executed by micro program 5) Variable instruction format 6) Many addressing modes 7) support complex addressing modes 8) single register set 9) not Pipelined or less

Interrupts
Interrupt is signal to the processor to indicate the event has occurred Corresponding to each interrupt their will be ISR that will be executed HALT the work Save the content of register and address by pushing onto the stack Interrupt vector- ISR address Execute IRS Reloads address and register contents by popping the stack There may be More than one interrupt to the processor Assign priority to each interrupt

 PIC- programmable interrupt controller interfaces with CPU to handle external devices and decide which interrupt has to be processed Interrupt vector table-address, number,priority,frequency NMI Non maskable interrupt ex-reset

Clock oscillatory circuit or clocking units

The clock controls the time for Executing the instruction Controls Clocking requirements of CPU , System timer, CPU machine cycle Machine cycle are for fetching the codes and data from memory and then decoding and executing them at the processor and transferring the results to the memory. For processing units, a highly stable oscillator is required and processor clock out signal provides the clock for synchronizing all system units with the processor

System Timers and Real time Clock

Timer circuit is suitably configured as system clock ,which ticks and generates system interrupt periodically For example 60 times per second ISR perform the required operation

REAL TIME CLOCK A timer circuit is suitably configured as RTC RTC generates system interrupt periodically for scheduler , real time program, for periodic saving of time and data in the system Used to obtain software control delays , timeout RTC acts as driver for timers

Watchdog timer(reset Circuit)

Most embedded system do not have reset button Due to software or hardware error , need to reset processor Reset button is provided in embedded system , on pressing the button reset signal is sent to the processor Watchdog timer does the resetting

Chip select
As many peripherals share common bus(memory chips/ input and output devices) Processor must uniquely identify a peripheral to communicate with it Processor performs this identification using a signal called chip select Chip select signal is available to all the peripherals connected to the bus

Function Keypad
Based on the application an embedded system has to be provided with function keypad to input data and/or commands

Led
Act as output devices Available in different colour RED,Green,yellow,blue,white Blue and white led are expensive Used for status display ,power failure indications etc

LCD-Liquid crystal display

A liquid crystal display (LCD) is a flat panel display, electronic visual display, or video display that uses the light modulating properties of liquid crystals. Liquid crystals do not emit light directly Used to display status information Display can be small as 1 line with 8 characters Other display can be of 6.4 inch or 8.4 inch Resolution can be 640*480 or 1024*768 new display technologies TFT Thin Film transistor High resolution,used in mobile phones

3 dimensional display OLED- Organic light emitting diode display Organic light emitting polymer is placed between anode and cathode When voltage is applied between anode and cathode OLED glows Much brighter display used in PDAs

Digital clock

Debug port
Manufacturers provide proprietary interfaces to do the debugging JTAG-JOINT TEST ACCESS GROUP Mechanism for providing a debugging through a port called JTAG PORT JTAG port provide access to the internal of the processor Standard IEEE 1149.1a-1993 ( standard test access port and boundary scan architecture) gives details of protocol used in JTAG port Using boundary scan technique the connection between processor and memory/peripherals can be probed by given appropriate signals at the output pins and regarding the response from input pins

1) 2) 3) 4)

Test data input (TDI) Test data output (TDO) Test mode select (TMS) Test clock (TCK)

JTAG port can also be used to download the software to embedded system

Communication Interfaces
For embedded system to extract with external world, a number of communication interfaces are provided Serial interface using RS232 Serial interface using Rs422/485 Universal serial bus Infrared Ethernet Wireless interface based on IEEE 802.11 wireless LAN standard Bluetooth radio interface

Direct memory access

Data transfer between I/O device and memory is coordinated by the CPU In case processor is busy Data transfer between I/O device and memory can take place directly, this is known as DMA A device called DMA controller does a job DMA controller takes control of the bus and transfer data between I/O device and memory

CPU

DMA Controller

Memory

I/O device

Inter integrated circuit

Serial clk

device

device

device

 Has two wires for connecting devices Bus is bidirectional, synchronous to common clock Built in in microcontroller Data rate-100kbps,400kbps are supported Bus consist of two lines 1) serial clock 2) Serial data High not in use The device using the bus drives the line low Each device has 7 bit unique address

128 devices can be connected A device can act as master or slave A device transmitting data -master receiving data-slave Bus is bidirectional Multiple master can be available We can interface a RTC such as philips pCF8353 Display device can be interfaced

Serial peripheral interface

Synchronous serial data link Operates in full duplex Named by Motorola Device communicate in master/slave mode Master initiates data frame Multiple slave devices are allowed with individual slave select(chip select lines) Sometimes SPI is called a four wire serial bus

The SPI bus specifies four logic signals: 1) SCLK: serial clock (output from master); 2) MOSI: master output, slave input (output from master); 3) MISO: master input, slave output (output from slave); 4) SS: slave select (active low, output from master).

The SPI bus can operate with a single master device and with one or more slave devices. If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it.

 Some slaves require the falling edge (high-low transition) of the chip select to initiate an action such as the Maxim MAX1242 ADC, which starts conversion on said transition. With multiple slave devices, an independent SS signal is required from the master for each slave device

Data transmission

 The bus master first configures the clock, using a frequency less than or equal to the maximum frequency the slave device supports. Such frequencies are commonly in the range of 1100 MHz. The master then transmits the logic 0 for the desired chip over chip select line If a waiting period is required (such as for analog-to-digital conversion), then the master must wait for at least that period of time before starting to issue clock cycles

During each SPI clock cycle, a full duplex data transmission occurs: the master sends a bit on the MOSI line; the slave reads it from that same line the slave sends a bit on the MISO line; the master reads it from that same line Transmissions normally involve two shift registers of some given word size, such as eight bits, one in the master and one in the slave; they are connected in a ring. Data is usually shifted out with the most significant bit first, while shifting a new least significant bit into the same register. After that register has been shifted out, the master and slave have exchanged register values.

Then each device takes that value and does something with it, such as writing it to memory. If there is more data to exchange, the shift registers are loaded with new data and the process repeats. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops toggling its clock. Normally, it then deselects the slave.

Power supply unit

Most systems have a power supply of their own. The supply has a specific operation range or a range of voltages. Various units in an embedded system operate in one of the following four operation ranges: (i) 5.0V + 0.25V (ii) 3.3V + 0.3V (iii) 2.0 + 0.2V (iv) 1.5V + 0.2V

 Additionally, a 12V + 0.2V supply is needed for a flash (a memory form used in systems like latest digital cameras) or Electrically Erasable and Programmable Read Only memory (EEPROM) when present in the microcontroller of an embedded system and for RS232C serial Interfaces

 Certain systems do not have a power source of their own: they connect to an external power supply or are powered by the use of charge pumps. (1) Network Interface Card (NIC) and Graphic Accelerator are examples of embedded systems that do not have their own power supply and connect to PC power-supply lines. (2) A charge pump consists of a diode in the series followed by a charging capacitor. The diode gets forward bias input from an external signal;