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Introduction to Computer Organization Unit 2

Computer Architecture
Central Processing Unit Memory Input/Output Most computer systems can be divided into three subsystems: the processor (known also as CPU), the memory and the Input/Output subsystem. The processor is responsible for executing programs, the memory is responsible for storage space for programs and data they reference and the I/O subsystem allows the processor to control devices that interact with outside world (such as CDROM, Monitor, Keyboard, etc..)

Generic Computer Organization

Von Neumann and Harvard architectures


Von Neumann
Allows instructions and data to be mixed and stored in the same memory module More flexible and easier to implement Suitable for most of the general purpose processors

Harvard:
Uses separate memory modules for instructions and for data It is easier to pipeline Higher memory throughput Suitable for DSP (Digital Signal Processors)

System buses
A bus is a set of wires, that interconnects all the components (subsystems) of a computer Source component sources out data onto the buss, the destination component inputs data from the bus A system may have a hierarchy of buses; The I/O controller may use a second bus, often described as I/O bus or local bus to access a variety of attached devices PCI bus is an example of a very common local bus

Address bus
CPU reads/writes data from the memory by addressing a specific location; outputs the location of the data on the address buss; memory uses the address to access the proper data Each I/O device (such as monitor, keypad, etc) has a unique address as well (or a range of addresses); when accessing a I/O device, CPU places its address on the address bus. Each device will detect if it is its own address and act accordingly Devices always receive the signlas from the CPU; CPU never reads the address buss (it is never addressed)

Data bus
When the CPU reads data from memory, it first outputs the address on the address bus, then the memory outputs the data onto the data bus; the CPU reads the data from data bus When writing data onto the memory, the CPU outputs first the address on the address bus, then outputs the data onto the output bus; memory then reads and stores the data at the proper location The process to read/write to a I/O device is similar

Control bus
Address and data buses consist of n lines, which combine to transmit one n bit value; control bus is a collection of individual control signals These signals indicate whether the data is to be read into or written out the CPU, whether the CPU is accessing memory or an IO device, and whether the I/O device or memory is ready for the data transfer This bus is mostly a collection of unidirectional signals

Instruction Cycle
1. 2. 3. 4. 5. 6. 7. Microprocessor places address of instruction on address bus Memory subsystem inputs address and decodes it After allowing time for address to be decoded, microprocessor issues a read control signal Data is placed on data bus Data is taken from data bus and placed in register Microprocessor decodes the instruction Instruction is executed

Memory Read

Memory Write

The Instruction Cycle

The Fetch cycle


The CPU puts an address of instruction on the address bus. The memory decodes the address to access the desired memory location. The CPU allows sufficient time for the memory to decode the address and sends a READ control signal. The READ signal is a signal on the Control bus which the CPU sends when its ready to read data from memory or I/O device. When the READ signal is asserted, the memory puts the instruction code to be fetched on to the data bus. The CPU inputs the data and stores it in one of its internal registers. The fetch cycle is completed.

The Instruction Cycle

The Decode cycle


The CPU decodes the instruction. Each instruction may require a different sequence of operations to execute the instruction. The CPU determines which instruction it is in order to select the correct sequence of operation to perform. This is done entirely within the CPU, it does not use the system buses.

The Instruction Cycle

The Execute cycle


The CPU executes the instruction. The execution may be: 1. 2. 3. 4. Read/write data to/from memory. Read/Write data to/from an I/O device. Perform only operations within the CPU. Perform some combination of the above.

CPU Internal Organization


READ, WRITE, IO/M

Program counter Instruction register General purpose


Instruction code Flag values Operations to perform

Types of Memory
Read Only Memory (ROM)
Masked ROM: programmed with data as chip is fabricated Programmable Read Only Memory (PROM): can be programmed by user, but only once Erasable PROM (EPROM): content can be erased and reprogrammed Electrically Erasable PROM (EEPROM): can modify individual locations on the EEPROM

Chip with 2n words, each having m bits, has n address inputs, An-1 to A0, and m data outputs, Dm-1 to D0 D is used as input to program chip Has chip enable (CE), output enable (OE), and program control input (Vpp) CE must be active for something to happen

Types of Memory
Random Access Memory (RAM)
Dynamic RAM (DRAM): like leaky capacitors, if not refreshed will eventually loose data. Used for primary memory. Static RAM (SRAM): Does not have to be refreshed. Faster than DRAM but more expensive. Used for cache memory.

Each 2n X m chip has n address inputs and m bidirectional data pins Chips have chip enable (CE or CE) Chips may have either read enable input (RD or RD) and write enable (WR or WR) or one combined signal, such as R/W . R/W would be set to 1 for read and 0 for write. CE must be active for read or write to happen

The Memory Subsystem (3)


Some systems want addresses to be aligned
address of a memory reference must be multiple of the size of data being read or written

Order in which the bytes are written to memory


Little endian systems (PC)
LSB written at lowest address byte

Big endian systems (Apple computers: G3, G4)


MSB written at lowest address byte

Little Endian

0x1000 ef

0x1001 cd

0x1002 ab

0x1002 90

Word: 0x90abcdef Address: 0x1000

Big Endian

90

ab

cd

ef

Memory read/write operations

a) Memory read operation b) Memory write operation

Memory
Types of ROM Chips

MROM

(Masked Read Only Memory)

Set by manufacturer and cannot be changed Mostly used on consumer appliances where large quantities are produced.

PROM

(Programmable Read Only Memory)

Programmable but only once Programmed by blowing internal fuses Mostly used for prototypes

Memory
Types of ROM Chips cont.
EPROM
(Erasable & Programmable ROM)

Totally erasable by exposing it to ultra violet light for over 20 minutes. Programmable outside the circuit.

EEPROM

(Electrically Erasable & Programmable ROM)

Electrically erasable. Able to erase a portion of the memory. Can be re programmed while in circuit. Mostly used for computer BIOS

FLASH Memory
Electrically erased, but it erases the entire memory.

Memory
Types of RAM Chips

DRAM
SRAM

(Dynamic Random Access Memory)

Widely used as main computer memory


(Static Random Access Memory)

Faster than DRAM More expensive than DRAM Mostly used in Cache memory

NVRAM

(Non Volatile Random Access Memory)

Does not lose data in memory when turned off. Contains an internal Lithium battery to retain power

Memory Chip Organization


The internal organization of ROM and RAM chips are similar. There are two organizations 1. Linear Organization 2. Two-Dimensional organization

Memory Chip Organization


Linear Organization
It is a simpler form of organization Used if few number of memory locations are needed

Internal Linear Organization of 8 X 2 ROM Chip Three address inputs, two data outputs, and 16 bits of internal storage arranged as eight 2-bit locations

The three addrss bits are decoded to select one of the eight locations

Memory Chip Organization

Two-dimensional Organization
Used to manage a large number of memory locations Allows large memory locations using fewer chips

Internal two-dimensional organization fo an 8 X 2 ROM chip

Two high order bits select one of the four rows, the low order bit selects the two desired bits

Four rows with four bits per row Top row holds bits for address 000 and 001, second row address 010 and 011

8 X 4 memory subsystem constructed from two 8 X 2 ROM chips

16 X 2 memory subsystem constructed from two 8 X 2 ROM chips with high-order interleaving

Upper chip always has A3 = 0 and the lower chip always has A3 = 1 Upper chip has addresses 0000 to 0111 Lower chip has addresses 1000 to 1111

16 X 2 memory subsystem constructed from two 8 X 2 ROM chips with low-order interleaving

Upper chip enabled for A0 = 0, or addresses 0, 2, 4, 6, 8, 10, 12, 14 Lower chip enabled for A0 = 1, or addresses 1, 3, 5, 7, 9, 11, 13, 15 Low order interleaving offers speed advantages for pipelined memory access

8 X 4 memory subsystem constructed from two 8 X 2 ROM chips with control signals

Output enable is just the RD signal from the CPU

6-bit address Use 3 low order bits for chip location Use 3 high order bits for chip enable (all must be 0 for chip to be active

Big Endian and Little Endian for value 01020304H

The I/O Subsystem


Contains devices that the computer uses to communicate with outside world and to store data I/O devices are usually communicating with the processor using and I/O bus
PCs are using PCI bus for their I/O bus OS needs a device driver to access a given I/O device
Program that allows the OS to control the I/O device

I/O read/write operations


The I/O read and write operations are similar to the memory read and write operations. A processor may use:
memory mapped I/O (when the address of the I/O device is in the direct memory space, and the sequence to read/write data in the device are the same with the memory read/write sequence) isolated I/O the process is similar, but the processor has a second set of control signals to make the distinction between a memory access and an I/O access (memory locations and I/O devices can be located at the same address, which makes this extra control signal necessary); for I/O operations, the processor holds IO/M (or similar) signal high for the duration of the I/O operation

Two types of I/O access


Memory mapped I/O Isolated I/O

Treats I/O device as if it were a memory location The same instructions are used to access both memory and I/O devices, but memory and the I/O device cannot both use the same address

Different instructions are used to access I/O devices and memory Requires an additional control line to distinguish between the two, but this allows memory and I/O devices to both use the same address

An Input Device

Interface

Enable logic for tri-state buffers I/O device address is 11110000

An Output Device

Tri-state buffers are not need for output because the data is put on the data bus and only the device at the address buss address will read the data from the data bus

Bidirectional input/output device with its interface and enable/load logic

A relatively simple computer, CPU details

A relatively simple computer, memory subsystem

A relatively simple computer, final design

A minimal 8085-based computer

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