Professional Documents
Culture Documents
Computer Architecture
Central Processing Unit Memory Input/Output Most computer systems can be divided into three subsystems: the processor (known also as CPU), the memory and the Input/Output subsystem. The processor is responsible for executing programs, the memory is responsible for storage space for programs and data they reference and the I/O subsystem allows the processor to control devices that interact with outside world (such as CDROM, Monitor, Keyboard, etc..)
Harvard:
Uses separate memory modules for instructions and for data It is easier to pipeline Higher memory throughput Suitable for DSP (Digital Signal Processors)
System buses
A bus is a set of wires, that interconnects all the components (subsystems) of a computer Source component sources out data onto the buss, the destination component inputs data from the bus A system may have a hierarchy of buses; The I/O controller may use a second bus, often described as I/O bus or local bus to access a variety of attached devices PCI bus is an example of a very common local bus
Address bus
CPU reads/writes data from the memory by addressing a specific location; outputs the location of the data on the address buss; memory uses the address to access the proper data Each I/O device (such as monitor, keypad, etc) has a unique address as well (or a range of addresses); when accessing a I/O device, CPU places its address on the address bus. Each device will detect if it is its own address and act accordingly Devices always receive the signlas from the CPU; CPU never reads the address buss (it is never addressed)
Data bus
When the CPU reads data from memory, it first outputs the address on the address bus, then the memory outputs the data onto the data bus; the CPU reads the data from data bus When writing data onto the memory, the CPU outputs first the address on the address bus, then outputs the data onto the output bus; memory then reads and stores the data at the proper location The process to read/write to a I/O device is similar
Control bus
Address and data buses consist of n lines, which combine to transmit one n bit value; control bus is a collection of individual control signals These signals indicate whether the data is to be read into or written out the CPU, whether the CPU is accessing memory or an IO device, and whether the I/O device or memory is ready for the data transfer This bus is mostly a collection of unidirectional signals
Instruction Cycle
1. 2. 3. 4. 5. 6. 7. Microprocessor places address of instruction on address bus Memory subsystem inputs address and decodes it After allowing time for address to be decoded, microprocessor issues a read control signal Data is placed on data bus Data is taken from data bus and placed in register Microprocessor decodes the instruction Instruction is executed
Memory Read
Memory Write
Types of Memory
Read Only Memory (ROM)
Masked ROM: programmed with data as chip is fabricated Programmable Read Only Memory (PROM): can be programmed by user, but only once Erasable PROM (EPROM): content can be erased and reprogrammed Electrically Erasable PROM (EEPROM): can modify individual locations on the EEPROM
Chip with 2n words, each having m bits, has n address inputs, An-1 to A0, and m data outputs, Dm-1 to D0 D is used as input to program chip Has chip enable (CE), output enable (OE), and program control input (Vpp) CE must be active for something to happen
Types of Memory
Random Access Memory (RAM)
Dynamic RAM (DRAM): like leaky capacitors, if not refreshed will eventually loose data. Used for primary memory. Static RAM (SRAM): Does not have to be refreshed. Faster than DRAM but more expensive. Used for cache memory.
Each 2n X m chip has n address inputs and m bidirectional data pins Chips have chip enable (CE or CE) Chips may have either read enable input (RD or RD) and write enable (WR or WR) or one combined signal, such as R/W . R/W would be set to 1 for read and 0 for write. CE must be active for read or write to happen
Little Endian
0x1000 ef
0x1001 cd
0x1002 ab
0x1002 90
Big Endian
90
ab
cd
ef
Memory
Types of ROM Chips
MROM
Set by manufacturer and cannot be changed Mostly used on consumer appliances where large quantities are produced.
PROM
Programmable but only once Programmed by blowing internal fuses Mostly used for prototypes
Memory
Types of ROM Chips cont.
EPROM
(Erasable & Programmable ROM)
Totally erasable by exposing it to ultra violet light for over 20 minutes. Programmable outside the circuit.
EEPROM
Electrically erasable. Able to erase a portion of the memory. Can be re programmed while in circuit. Mostly used for computer BIOS
FLASH Memory
Electrically erased, but it erases the entire memory.
Memory
Types of RAM Chips
DRAM
SRAM
Faster than DRAM More expensive than DRAM Mostly used in Cache memory
NVRAM
Does not lose data in memory when turned off. Contains an internal Lithium battery to retain power
Internal Linear Organization of 8 X 2 ROM Chip Three address inputs, two data outputs, and 16 bits of internal storage arranged as eight 2-bit locations
The three addrss bits are decoded to select one of the eight locations
Two-dimensional Organization
Used to manage a large number of memory locations Allows large memory locations using fewer chips
Two high order bits select one of the four rows, the low order bit selects the two desired bits
Four rows with four bits per row Top row holds bits for address 000 and 001, second row address 010 and 011
16 X 2 memory subsystem constructed from two 8 X 2 ROM chips with high-order interleaving
Upper chip always has A3 = 0 and the lower chip always has A3 = 1 Upper chip has addresses 0000 to 0111 Lower chip has addresses 1000 to 1111
16 X 2 memory subsystem constructed from two 8 X 2 ROM chips with low-order interleaving
Upper chip enabled for A0 = 0, or addresses 0, 2, 4, 6, 8, 10, 12, 14 Lower chip enabled for A0 = 1, or addresses 1, 3, 5, 7, 9, 11, 13, 15 Low order interleaving offers speed advantages for pipelined memory access
8 X 4 memory subsystem constructed from two 8 X 2 ROM chips with control signals
6-bit address Use 3 low order bits for chip location Use 3 high order bits for chip enable (all must be 0 for chip to be active
Treats I/O device as if it were a memory location The same instructions are used to access both memory and I/O devices, but memory and the I/O device cannot both use the same address
Different instructions are used to access I/O devices and memory Requires an additional control line to distinguish between the two, but this allows memory and I/O devices to both use the same address
An Input Device
Interface
An Output Device
Tri-state buffers are not need for output because the data is put on the data bus and only the device at the address buss address will read the data from the data bus