Chapter 05 - Msp430 Isa

Chapter 5 MSP430 ISA The Instruction Set
Topics to Cover

MSP430 ISA Assembler Primer Instruction Formats Double Operand Instructions Single Operand Instructions Jump Instructions Addressing Modes Instruction Length Instruction Cycles Instruction Disassembly
Chapter 05 - MSP430 ISA 2
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Levels of Transformation
Problem Machine
Abstract, machine-independent; easier to write, read, debug, maintain More concrete, machine-dependent; error prone, harder to write, read, debug, maintain
Problem
Algorithm
High-level language statements

lampDoesntWork() { if(unPlugged) { plugin(); } else if(burnedOut) { replace(); } else { buyNewLamp(); } }
Assembly language instructions

MOV.B 0x0001(SP),R14 MOV.W SP,R15 INCD.W R15 ADD.W R15,R14 MOV.B @R14,0x0000(SP) MOV.B 0x0001(SP),R14 INC.W R14 MOV.W SP,R15 INCD.W R15 ADD.W R15,R14 MOV.B 0x0001(SP),R13 MOV.W SP,R15 INCD.W R15 ADD.W R15,R13 MOV.B @R14,0x0000(R13) MOV.B 0x0001(SP),R15 INC.W R15 MOV.W SP,R14 INCD.W R14 ADD.W R15,R14 MOV.B @SP,0x0000(R14)
Machine language instructions

415E 0001 410F 532F 5F0E 4EE1 0000 415E 0001 531E 410F 532F 5F0E 415D 0001 410F 532F 5F0D 4EED 0000 415F 0001 531F 410E 532E 5F0E 41EE 0000
Problem
Problem solved by Algorithm
One algorithm = Many statements Chapter 05 - MSP430 ISA
One statement = Many instructions
Assembler
Engineer
Compiler
Coder
Instruction = Many cycles 3
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MSP430 ISA
Instruction Set Architecture
The computer ISA defines all of the programmer-visible components and operations of the computer
Memory organization address space -- how may locations can be addressed? addressibility -- how many bits per location? Register set how many? what size? how are they used? Instruction set opcodes data types addressing modes
ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language).
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MSP430 ISA
MSP430 ISA
RISC/CISC machine 27 orthogonal instructions

8 jump instructions 7 single operand instructions 12 double operand instructions
4 basic addressing modes. 8/16-bit instruction addressing formats. Memory architecture 16 16-bit registers 16-bit Arithmetic Logic Unit (ALU). 16-bit address bus (64K address space) 16-bit data bus (8-bit addressability) 8/16-bit peripherals
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Chapter 05 - MSP430 ISA
MSP430 ISA
MSP430 Registers
R0 (PC) Program Counter

Points to (has the address of) the next instruction to be fetched. Each instruction occupies an even number of bytes. Therefore, the least significant bit (LSB) of the PC register is always zero. After executing an instruction, the PC register will have incremented by 2, 4, or 6 and point to the next instruction.
R1 (SP) Stack Pointer
The MSP430 CPU pushes the return address of subroutine calls and interrupts on the stack. User programs store local data on the stack. The SP can be incremented or decremented automatically with each stack access. The stack grows down thru RAM and thus SP must be initialized with a valid RAM address. SP always points to an even address, so its LSB is always zero.
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MSP430 ISA
MSP430 Registers
R2 (SR/CG1) Status Register

The status of the MSP430 CPU is found in register R2. Only accessible through register addressing mode - all other addressing modes are reserved to support the constant generator.
V Overflow bit
SCG1
SCG0 OSCOFF CPUOFF GIE N Z C
Turns off the SMCLK.

Turns off the DCO dc generator. Oscillator off Turns off the CPU. General interrupt enable Negative bit Zero bit Carry bit
R3 (CG2) Constant Generator

Register R2 R2 R2 R2 R3 R3 R3 R3 As 00 01 10 11 00 01 10 11 Constant (0) 00004h 00008h 00000h 00001h 00002h 0FFFFh Remarks Register mode Absolute mode +4, bit processing +8, bit processing 0, word processing +1 +2, bit processing -1, word processing
R4-R15 General Purpose registers

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MSP430 ISA
MSP430 ALU
16 bit Arithmetic Logic Unit (ALU).
Performs instruction arithmetic and logical operations. Instruction execution affects the state of the following flags:

Zero (Z) Carry (C) Overflow (V) Negative (N)
The MCLK (Master) clock signal drives the CPU and ALU logic.
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MSP430 ISA
MSP430 Memory Organization
A little-endian machine stores the least significant byte first (lowest address) within a word data type.
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MSP430 ISA
Quiz 5.1
Pair up with another student and answer the following questions: 1. What is an ISA?
2. List distinctive properties of the MSP430 ISA.
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MSP430 ISA
Quiz 5.1 (answers)

Pair up with another student and answer the following questions: 1. What is an ISA?
All of the programmer-visible components and operations of the computer
2. List distinctive properties of the MSP430 ISA.

27 orthogonal instructions 7 addressing modes. 8/16-bit addressing formats. 16 16-bit registers Constant generator
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16-bit Arithmetic Logic Unit (ALU). 16-bit address bus (64K address space) 16-bit data bus (8-bit addressability) 8/16-bit peripherals Little-endian storage order
11
Assembler Primer
MSP430 Assembler
A typical assembly language line has four parts:

start: Label: mov.w Operation #0x0280,sp Operands ; setup stack pointer Comment
1. labelstarts in the column 1 and may be followed by a colon (:) for clarity. 2. operationeither an instruction, which is translated into binary machine code for the processor itself, or a directive, which controls the assembler. 3. operandsdata needed for this operation (not always required). 4. commenttext following a semicolon (;).
Assembler Primer
MSP430 Assembler
Labels are case sensitive, but instructions and directives are not - pick a style and stick with it. Use comments freely in assembly language otherwise your program is unreadable and very difficult to debug. The default base (radix) of numbers in assembly language is decimal. The C-style notation 0xA5 for hexadecimal numbers is now widely accepted by assemblers. Other common notations include $A5, h'A5' and 0A5h. Binary numbers can similarly be written as 10100101b. Use symbolic names for constants and expressions. The ".equ" and ".set" assembler directives provide macro text replacement for this purpose. (Make upper case.)
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Assembler Primer
Assembler Coding Style

Instructions / DIRECTIVES start in column 12. Labels start in column 1 and are 10 characters or fewer. Operands start in column 21. Comments start in column 45. No line should exceed 80 characters. ;************************************************************************* ; CS/ECEn 124 Lab 1 - blinky.asm: Software Toggle P1.0 ; ; Description: Toggle P1.0 by xor'ing P1.0 inside of a software loop. ;************************************************************************* DELAY .equ 0 .cdecls C,"msp430.h" ; MSP430 .text ; beginning of executable code reset: mov.w #0x0280,SP ; init stack pointer mov.w #WDTPW+WDTHOLD,&WDTCTL ; stop WDT Begin writing your The ".cdecls" directive bis.b #0x01,&P1DIR ; set P1.0 as output assembly code after inserts a header file the ".text" directive. into your program. mainloop: xor.b #0x01,&P1OUT ; toggle P1.0 mov.w #DELAY,r15 ; use R15 as delay counter delayloop: Instructions are lower case and macros are UPPER CASE. sub.w jnz jmp .sect .word .end #1,r15 delayloop mainloop ".reset" reset Use macros provided in ; delay over? the MSP430 header file. ; n ; y, toggle led ; MSP430 RESET Vector ; start address Assembler directives begin with a period (.)
The ".end" directive is the last line of your program.
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Instruction Formats
MSP430 Instructions
There are three formats used to encode instructions for processing by the CPU core:

Double operand Single operand Jumps
The instructions for double and single operands, depend on the suffix used, (.w) word or (.b) byte These suffixes allow word or byte data access If the suffix is ignored, the instruction processes word data by default
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Instruction Formats
MSP430 Instructions
The MSP430 ISA uses three formats to encode instructions for processing by the CPU core:

Double operand Single operand Jumps
Single and double operand instructions process word (16-bits) or byte (8-bit) data operations.

Instruction suffix selects word (.w) or byte (.b) Instructions process word data by default.
The first 4-bits (nybble) of an instruction is called the opcode and specifies the instruction format.
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Instruction Formats
MSP430 Instructions
Memory
0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0
mov.w r5,r4 rrc.w r5 jc main
PC
0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1
0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0
Instruction Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
mov.w #0x0600,r1
0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0
Opcode
4 to 16 Decoder
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Opcode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Instruction Undefined RCC, SWPB, RRA, SXT, PUSH, CALL, RETI JNE, JEQ, JNC, JC JN, JGE, JL, JMP MOV ADD ADDC SUBC SUB CMP DADD BIT BIC BIS XOR AND
Format Single Operand Jumps
Double Operand
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MSP430 Instructions
MPS430 Instruction Formats
Format I: Instructions with two operands:

15 14 13 12 11 10 9 8 7
Ad
6
b/w
5
As
Opcode
S-reg
D-reg
Format II: Instruction with one operand:

15 14 13 12 11 10 9 8 7 6 b/w 5 Ad 4 3 2 1 0 Opcode D/S-reg
Format III: Jump instructions:

15 14
Opcode
13
12
11
10
Condition
10-bit, 2s complement PC offset
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Double Operand Instructions
Format I: Double Operand
Double operand instructions:

Operation
src+dstdst src+dst+Cdst src+dst+Cdst (dec) dst+.not.src+1dst dst+.not.src+Cdst src.and.dstdst .not.src.and.dstdst src.or.dstdst src.and.dst src.xor.dstdst
Mnemonic
Arithmetic instructions ADD(.B or .W) src,dst ADDC(.B or .W) src,dst DADD(.B or .W) src,dst SUB(.B or .W) src,dst SUBC(.B or .W) src,dst
Description
Add source to destination Add source and carry to destination Decimal add source and carry to destination Subtract source from destination Subtract source and not carry from destination
Logical and register control instructions AND(.B or .W) src,dst BIC(.B or .W) src,dst BIS(.B or .W) src,dst BIT(.B or .W) src,dst XOR(.B or .W) src,dst Data instructions CMP(.B or .W) src,dst MOV(.B or .W) src,dst dst-src srcdst Compare source to destination Move source to destination AND source with destination Clear bits in destination Set bits in destination Test bits in destination XOR source with destination
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Double Operand Instructions
Example: Double Operand
Copy the contents of a register to another register

Assembly: mov.w r5,r4 Instruction code: 0x4504

Opcode mov S-reg r5 Ad Register b/w 16-bits As Register D-reg r4
0100
0101
00
0100
One word instruction The instruction instructs the CPU to copy the 16-bit 2s complement number in register r5 to register r4
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Single Operand Instructions
Format II: Single Operand
Single operand instructions:

Operation MSBMSB LSBC CMSBLSBC Swap bytes bit 7bit 8bit 15 Description Roll destination right Roll destination right through carry Swap bytes in destination Sign extend destination Push source on stack Subroutine call to destination
Mnemonic RRA(.B or .W) dst RRC(.B or .W) dst SWPB( or .W) dst SXT dst
Logical and register control instructions
PUSH(.B or .W) src SP-2SP, src@SP Program flow control instructions CALL(.B or .W) dst SP-2SP, PC+2@SP dstPC RETI
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@SP+SR, @SP+SP
Return from interrupt

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Single Operand Instructions
Example: Single Operand
Logically shift the contents of register r5 to the right through the status register carry

Assembly: rrc.w r5 Instruction code: 0x1005
Opcode rrc
000100000

b/w 16-bits
0
Ad Register
00
D-reg r5
0101
One word instruction The CPU shifts the 16-bit register r5 one bit to the right (divide by 2) the carry bit prior to the instruction becomes the MSB of the result while the LSB shifted out replaces the carry bit in the status register
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Jump Instructions
Jump Instruction Format

15 14 Opcode
13
12
11
10
Condition
10-bit, 2s complement PC offset
Jump instructions are used to direct program flow to another part of the program. The condition on which a jump occurs depends on the Condition field consisting of 3 bits:

000: jump if not equal 001: jump if equal 010: jump if carry flag equal to zero 011: jump if carry flag equal to one 100: jump if negative (N = 1) 101: jump if greater than or equal (N = V) 110: jump if lower (N V) 111: unconditional jump
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Jump Instructions
Jump Instruction Format
Jump instructions are executed based on the current PC and the status register Conditional jumps are controlled by the status bits Status bits are not changed by a jump instruction The jump off-set is represented by the 10-bit, 2s complement value:
PCnew PCold 2 PCoffset 2
Thus, the range of the jump is -511 to +512 words, (-1023 to 1024 bytes ) from the current instruction Note: Use a BR instruction to jump to any address
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Jump Instructions
Example: Jump Format
Continue execution at the label main if the carry bit is set

Assembly: jc main Instruction code: 0x2fe4

Opcode JC 001 Condition Carry Set 011 10-Bit, 2s complement PC offset -28 1111100100
One word instruction The CPU will add to the incremented PC (R0) the value -28 x 2 if the carry is set
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Today
Exam I

Thursday, Feb 7 thru Monday, Feb 11 Testing Center, Grant Building 60 Questions, Chapters 1 through 5 50% penalty if you miss exam Good idea to have scratch paper on hand 1 page, handwritten notes Take the pre-test exam!! Study slides, homework, and reading material
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MSP430 Instructions
Quiz 5.2
1. How are the sixteen MSP430 registers the same? 2. How do they differ? 3. What does 8-bit addressibility mean? 4. Why does the MSP430 have a 16-bit data bus? 5. What does the following instruction do?
addc.w
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r11,r12
MSP430 Instructions
Quiz 5.2 (answers)

1. How are the sixteen MSP430 registers the same?
16-bits, orthogonal, single cycle access
2. How do they differ?

4 special, 12 work
3. What does 8-bit addressibility mean?

Smallest accessible size of memory
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MSP430 Instructions
Quiz 5.2 (answers)

4. Why does the MSP430 have a 16-bit data bus?
Speed! Convenient for instruction and stack access
5. What does the following instruction do?

addc.w r11,r12 Fetches the contents of registers r11, r12, and the carry bit, uses the ALU to sum these values, and stores the results back in register r12.
MSP430 Addressing Modes
Addressing Modes
MPS430 Addressing Modes

1 2 3 000 4 5 8000 6 8002 8004 7 8006 8 8008 9 800a 800c 10 800e 8010 11 8012 8014 12 8016 13 8018 801a 801c 14 15 801e 16 8020 ;**************************************************** .cdecls C,"msp430.h" ; MSP430 .text Register 540A 541A 0006 542A 543A 501A 0012 521A 801E 503A 0064 531A 5090 0004 0004 0000 0000 reset: add.w add.w add.w add.w add.w add.w add.w add.w add.w r4,r10 6(r4),r10 @r4,r10 @r4+,r10 cnt,r10 &cnt,r10 #100,r10 #1,r10 cnt,var ; r10 = r4 + r10 Indirect Register ; r10 = M(r4+6) + r10 ; r10 = M(r4) Symbolic + r10 or PC ; r10 = M(r4++) + r10 relative ; r10 = M(cnt) + r10 ; r10 = M(cnt) + r10 ; r10 = 100 + r10
Indexed Register
Indirect Auto-inc
Absolute Immediate Constant
; r10 = 1 + r10 ; var = M(cnt) + M(var)
cnt: var:
.word .word
0 0 Chapter 05 - MSP430 ISA 31
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Addressing Modes
Source Addressing Modes
The MSP430 has four basic addressing modes for the source address:

00 = Rs - Register 01 = x(Rs) - Indexed Register 10 = @Rs - Register Indirect 11 = @Rs+ - Indirect Auto-increment
When used in combination with registers R0-R3, three additional source addressing modes are available:

label - PC Relative, x(PC) &label Absolute, x(SR) #n Immediate, @PC+

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Addressing Modes
Destination Addressing Modes
There are only two basic addressing modes for the destination address:

0 = Rd - Register 1 = x(Rd) - Indexed Register
When used in combination with registers R0/R2, two additional destination addressing modes are available:

label - PC Relative, x(PC) &label Absolute, x(SR)
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Addressing Modes
00 = Register Mode
add.w r4,r10
Memory PC PC
0x540a 0x540a IR
;r10 = r4 + r10
CPU
Registers
PC R4
ADDER
+2
R10
ALU
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Addressing Modes
01 = Indexed Mode
add.w 6(r4),r10 ;r10 = M(r4+6) + r10
Memory PC PC PC
0x541a 0x0006 0x541a IR
CPU
Registers
PC R4
ADDER
+2
R10
ALU
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Addressing Modes
10 = Indirect Register Mode

add.w @r4,r10
Memory PC PC
0x542a 0x542a IR
;r10 = M(r4) + r10

CPU
Registers
PC R4
ADDER
+2
R10
ALU
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Addressing Modes
11 = Indirect Auto-increment Mode

add.w @r4+,r10
Memory PC PC
0x543a 0x543a IR
;r10 = M(r4+) + r10

CPU
Registers
PC
+2
0002
R4
ADDER
R10
ALU
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Addressing Modes
01 w/R0 = Symbolic Mode (PC Relative)

add.w cnt,r10
Memory PC PC PC
0x501a 0x000c 0x501a IR
;r10 = M(cnt) + r10

CPU
Registers
PC
+2
ADDER
cnt
R10
ALU
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Addressing Modes
01 w/R2 = Absolute Mode

add.w &cnt,r10
Memory PC PC PC
0x521a 0xc018 0x521a IR
;r10 = M(cnt) + r10

CPU
Registers
PC
+2
0000
ADDER
cnt
R10
ALU
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Addressing Modes
11 w/R0 = Immediate Mode

add.w #100,r10
Memory PC PC PC
0x503a 0x0064 0x503a IR
;r10 = 100 + r10

CPU
Registers
PC
+2
ADDER
R10
ALU
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Addressing Modes
Constant Generator
add.w #1,r10
Memory PC PC
0x531a 0x531a IR
;r10 = #1 + r10
CPU
Registers
0000 0001 0002 0004 0008 ffff
PC
+2
ADDER
R10
ALU
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Addressing Modes
3 Word Instruction (6 cycles)

add.w cnt,var
Memory
PC PC PC
0x5090 0x000c 0x0218 0x5090 IR Data Bus (+1 cycle) Data Bus (+1 cycle)
ADDER
;var = M(cnt) + M(var)

CPU
Registers
PC
+2
PC cnt
Address Bus
var
Data Bus (+1 cycle)
ALU
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Instruction Length
MSP430 Instructions
Instruction Length
1 word for instruction

Format I:
Format II: Format III:
15 14 13 12 11 10 9 Opcode S-reg 15 14 13 12 11 10 Opcode 15 14 13 Opcode 9
8 8
7 6 5 4 Ad b/w As 7 6 5 4 b/w Ad
3 3
2 1 D-reg
2 1 0 D/S-reg
12 11 10 9 8 7 6 5 4 3 2 1 0 Condition 10-bit, 2s complement PC offset
1 additional word for each of the following addressing modes: mov 10(r4),r5
Source index mode (As = 01) Source immediate mode (As = 11, SR = PC) Destination index mode (Ad = 1)
mov cnt,r5 mov &P1IN,r5 mov #100,r5 mov r4,10(r5) mov r4,cnt mov r4,&P1OUT
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Instruction Length
Quiz 5.3
What is the length (in words) for each of the following instructions?
Instruction add.w r5,r6 add.w cnt(r5),r6 add.w @r5,r6 add.w @r5+,r6 add.w cnt,r6 add.w &cnt,r6 add.w #100,r6 mov.w r10,r11 mov.w @r5,6(r6) mov.w 0(r5),6(r6) L
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
11. 12. 13. 14. 15. 16. 17. 18. 19. 20.
Instruction mov.w EDE,TONI mov.b &MEM,&TCDAT mov.w @r10,r11 mov.b @r10+,tab(r6) mov.w #45,TONI mov.w #2,&MEM mov.b #1,r11 mov.w #45,r11 mov.b #-1,-1(r15) mov.w @r10+,r10
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Chapter 6 - MSP430 Microarchitecture
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Instruction Length
Quiz 5.3 (solution)
What is the length (in words) for each of the following instructions?
Instruction add.w r5,r6 add.w cnt(r5),r6 add.w @r5,r6 add.w @r5+,r6 add.w cnt,r6 add.w &cnt,r6 add.w #100,r6 mov.w r10,r11 mov.w @r5,6(r6) mov.w 0(r5),6(r6) L 1 2 1 1 2 2 2 1 2 3
1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
11. 12. 13. 14. 15. 16. 17. 18. 19. 20.
Instruction mov.w EDE,TONI mov.b &MEM,&TCDAT mov.w @r10,r11 mov.b @r10+,tab(r6) mov.w #45,TONI mov.w #2,&MEM mov.b #1,r11 mov.w #45,r11 mov.b #-1,-1(r15) mov.w @r10+,r10
L 3 3 1 2 3 2 1 2 2 1
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Instruction Clock Cycles
Cycles Per Instruction...
Instruction timing:

1 cycle to fetch instruction word +1 cycle if source is @Rn, @Rn+, or #Imm +2 cycles if source uses indexed mode

1st to fetch base address 2nd to fetch source Includes absolute and symbolic modes
+2 cycles if destination uses indexed mode +1 cycle if writing destination back to memory +1 cycle if writing to PC (R0) Jump instructions are always 2 cycles
Blinky Lab 47
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Example Cycles/Length...
Example add R5,R8 Src Rn Dst Rm Cycles Length 1 1
add @R5,R6
mov @R5+,R0 add R5,4(R6)
@Rn
@Rn+ Rn
Rm
PC x(Rm)
2
3 4
1
1 2
add R8,EDE
add R5,&EDE add #100,TAB(R8)
Rn
Rn #n #1
EDE
&EDE x(Rm) &EDE
Blinky Lab
4
4 5
2
2 3
add &TONI,&EDE
add #1,&EDE
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&TONI &EDE
6
4
3
2
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Quiz 5.4
;******************************************************************************* ; CS/ECEn 124 Lab 3 - blinky.asm ;******************************************************************************* ; cycles = --; MCLK = --- cycles / 10 seconds = --- Mhz ; CPI = MCLK / --; MIPS = MCLK / CPI / 1000000 = --- MIPS .cdecls C,LIST, "msp430.h" ; MSP430 COUNT .equ 0 ; delay count ;-----------------------------------------------------------------------------.text ; beginning of executable code ;-----------------------------------------------------------------------------RESET: mov.w #0x0280,SP ; init stack pointer mov.w #0x5a80,&0x0120 ; stop WDT (WDTCTL) bis.b #0x01,&0x0022 ; set P1.0 as output (P1DIR) mainloop: delayloop: xor.b mov.w sub.w jnz jmp #0x01,&0x0021 #COUNT,r15 #1,r15 delayloop mainloop ; ; ; ; ; toggle P1.0 (P1OUT) use R15 as delay counter delay over? n y, toggle led
How many cycles for each instruction?
;-----------------------------------------------------------------------------; Interrupt Vectors ;-----------------------------------------------------------------------------.sect ".reset" ; MSP430 RESET Vector .word RESET ; start address .end
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Blinky Lab
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Quiz 5.4 (solution)

;******************************************************************************* ; CS/ECEn 124 Lab 3 - blinky.asm ;******************************************************************************* ; cycles = --; MCLK = --- cycles / 10 seconds = --- Mhz ; CPI = MCLK / --; MIPS = MCLK / CPI / 1000000 = --- MIPS .cdecls C,LIST, "msp430.h" ; MSP430 COUNT .equ 0 ; delay count ;-----------------------------------------------------------------------------.text ; beginning of executable code ;-----------------------------------------------------------------------------RESET: mov.w #0x0280,SP ; 2 init stack pointer mov.w #0x5a80,&0x0120 ; 5 stop WDT (WDTCTL) bis.b #0x01,&0x0022 ; 4 set P1.0 as output (P1DIR) mainloop: delayloop: xor.b mov.w sub.w jnz jmp #0x01,&0x0021 #COUNT,r15 #1,r15 delayloop mainloop ; 4 ; 1 ; 1 ; 2 ; 2 toggle P1.0 (P1OUT) use R15 as delay counter delay over? n y, toggle led
How many cycles for each instruction?
;-----------------------------------------------------------------------------; Interrupt Vectors ;-----------------------------------------------------------------------------.sect ".reset" ; MSP430 RESET Vector .word RESET ; start address .end
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Blinky Lab
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Quiz 5.5
Given a 1.2 MHz processor, what value for DELAY would result in a 1/4 second delay?
DELAY .equ ???
mov.w
delay1: delay2: mov.w sub.w jne sub.w jne
#DELAY,r12
#1000,r15 #1,r15 delay2 #1,r12 delay1
;
; ; ; ; ;
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Quiz 5.5 (solution)
Given a 1.2 MHz processor, what value for DELAY would result in a 1/4 second delay?
DELAY .equ ???
mov.w
delay1: delay2: mov.w sub.w jne sub.w jne
#DELAY,r12
#1000,r15 #1,r15 delay2 #1,r12 delay1
; 2 cycles
; 2 cycles
cycle 2 + DELAY (2 + 3000 + 1 + 2) cycles cycle cycles 300000 2 1 second = 1,200,000 cycles DELAY = ---------0.25 seconds = 1,200,000 / 4 = 300,000 cycles 3005 = 99.833 = 100 300,000 cycles = 2 + (DELAY x 3005) cycles
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; 3000 ; ; ;
1 2 1 2
Disassembling Instructions
Instruction Disassembly
How to Disassemble MSP430 Code

1. Begin with a PC pointing to the first word in program memory. 2. Retrieve instruction word and increment PC by 2. 3. Find and list the corresponding instruction mnemonic using the opcode (most significant 4-9 bits). 4. Append .b or .w using the b/w bit (0=word, 1=byte). 5. If double operand instruction, decode and list source operand (Table 5). 6. If single or double operand instruction, decode and list destination operand (Tables 3 and 5). 7. If jump instruction, sign extend the 10-bit PC offset, multiply by 2, and add to the current PC. List that address.

1. 2. Begin with a PC pointing to the first word in program memory. Retrieve instruction word and increment PC by 2.
R0 R0
0xf800: 0xf802: 0xf804: 0xf806: 0xf808: 0xf80a: 0xf80c: 0xf80e: 0xf810: 0xf812: 0xf814: 0xf816: 0xf818:
4031 0100 0000 0011 0001 0280 40b2 5a80 0120 d3d2 0022 e3d2 0021 430f 831f 23fe 3ffa
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3. 4. Find and list the corresponding instruction mnemonic using the opcode (most significant 4-9 bits). Append .b or .w using the b/w bit when appropriate (0=w, 1=b).
R0
4031 0100 0000 0011 0001 0280 40b2 5a80 0120 d3d2 0022 e3d2 0021 430f 831f 23fe 3ffa
mov .w
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56

5. If double operand instruction, decode and list source operand.
15 14 13 12 11 10 9 Opcode S-reg 8 7 6 5 4 Ad b/w As 3 2 1 D-reg 0
R0 R0
4031 0100 0000 0011 0001 0280 40b2 5a80 0120 d3d2 0022 e3d2 0021 430f 831f 23fe 3ffa
mov.w # 0x0280 mov
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6. If single or double operand instruction, decode and list destination operand. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Opcode S-reg Ad b/w As D-reg
R0
4031 0100 0000 0011 0001 0280 40b2 5a80 0120 d3d2 0022 e3d2 0021 430f 831f 23fe 3ffa
mov.w # 0x0280 ,r1 mov
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Repeat process for next instruction.
R0
4031 0100 0000 0011 0001 0280 40b2 0100 0000 1011 0010 5a80 0120 d3d2 0022 e3d2 0021 430f 831f 23fe 3ffa
mov.w # 0x0280,r1 mov
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59
Addressing Modes
Address Mode Register 0 Symbolic Indexed Absolute +1 Indirect +4 +2 Immediate Indirect auto-inc +8 -1 As 00 00 01 01 01 01 10 10 10 11 11 11 11 Registers
R0-R2, R4-R15 R3 R0 R1, R4-R15 R2 R3 R0-R1,R4-R15 R2 R3 R0 R1,R4-R15 R2 R3
Syntax
Rn #0 ADDR X(Rn) &ADDR #1 @Rn #4 #2 #N @Rn+ #8 #-1
Operation
Register Contents. 0 Constant source / bit bucket destination (PC+next word) points to operand. (X(PC)) (Rn+X) points to operand. X is next code word. Next code word is the absolute address. (X(SR)) +1 Constant Rn points to operand. +4 Constant +2 Constant Next word is the constant N. (@PC+) Rn points to operand, Rn is incremented (1 or 2). +8 Constant -1 Constant
Destination
Source
Address Mode Register Symbolic Indexed Absolute -
Ad 0 1 1 1 -
Registers
R0-R2, R4-R15 R0 R1, R4-R15 R2 R3
Syntax
Rn ADDR X(Rn) &ADDR -
Operation
Register Contents. (PC+next word) points to operand. (X(PC)) (Rn+X) points to operand. X is next code word. Next code word is the absolute address. (X(SR)) Undefined
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Quiz 5.6
Disassemble the following MSP430 instructions:

Address 0x8010: 0x8012: 0x8014: 0x8016: 0x8018: 0x801a: 0x801c: 0x801e: 0x8020: 0x8022: 0x8024: 0x8026: 0x8028: 0x802a: 0x802c: 0x802e: Data 4031 0600 40B2 5A1E 0120 430E 535E F07E 000F 1230 000E 8391 0000 23FD 413F 3FF6
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Quiz 5.6 (solution)

Address 0x8010: 0x8012: 0x8014: 0x8016: 0x8018: 0x801a: 0x801c: 0x801e: 0x8020: 0x8022: 0x8024: 0x8026: 0x8028: 0x802a: 0x802c: 0x802e: Data mov.w #0x0600,r1 4031 0100 0000 0 0 11 0001 0600 40B2 0=word, 1=byte 5A1E 0120 mov instruction 430E 535E mode SR=PC, DR=R1, indirect,register auto-inc mode F07E (immediate) 000F 1230 000E 8391 0000 23FD 413F 3FF6
R0 R0 R0
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Quiz 5.6 (solution)

Address 0x8010: 0x8012: 0x8014: 0x8016: 0x8018: 0x801a: 0x801c: 0x801e: 0x8020: 0x8022: 0x8024: 0x8026: 0x8028: 0x802a: 0x802c: 0x802e: Data mov.w #0x0600,r1 4031 0100 0000 0 0 11 0001 0600 mov.w #0x5a1e,&0x0120 40B2 0100 0000 1 0 11 0010 5A1E 0120 0=word, 1=byte 430E 535E mov instruction F07E 000F DR=R2, mode SR=PC, indexed indirect,register auto-inc mode 1230 (Absolute) (immediate) 000E 8391 0000 23FD 413F 3FF6
R0 R0 R0 R0
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Quiz 5.6 (solution)

Address 0x8010: 0x8012: 0x8014: 0x8016: 0x8018: 0x801a: 0x801c: 0x801e: 0x8020: 0x8022: 0x8024: 0x8026: 0x8028: 0x802a: 0x802c: 0x802e: Data mov.w #0x0600,r1 4031 0100 0000 0 0 11 0001 0600 mov.w #0x5a1e,&0x0120 40B2 0100 0000 1 0 11 0010 5A1E 0120 430E 0100 0011 0 0 00 1110 mov.w #0,r14 535E F07E 0=word, 1=byte 000F 1230 mov instruction 000E 8391 DR=R14, SR=R3, Register Constant mode 0 0000 23FD 413F 3FF6
R0 R0
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Quiz 5.6 (solution)

0100 0000 0 0 11 0001 0100 0000 1 0 11 0010 0100 0011 0 0 00 1110 0101 0011 0 1 01 1110 mov.w #0x0600,r1 mov.w #0x5a1e,&0x0120 mov.w #0,r14 add .b #1,r14
R0 R0
0=word, 1=byte add instruction DR=R14, SR=R3, Register Constant mode 1

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Quiz 5.6 (solution)

0100 0000 0 0 11 0001 0100 0000 1 0 11 0010 0100 0011 0 0 00 1110 0101 0011 0 1 01 1110 1111 0000 0 1 11 1110 mov.w #0x0600,r1 mov.w #0x5a1e,&0x0120 mov.w #0,r14 add.b #1,r14 and .b #0x000f ,r14
R0 R0 R0
0=word, 1=byte and instruction mode SR=PC, DR=R1, indirect,register auto-inc mode (immediate)
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Quiz 5.6 (solution)

0100 0000 0 0 11 0001 0100 0000 1 0 11 0010 0100 0011 0 0 00 1110 0101 0011 0 1 01 1110 1111 0000 0 1 11 1110 0001 00100 0 11 0000 mov.w #0x0600,r1 mov.w #0x5a1e,&0x0120 mov.w #0,r14 add.b #1,r14 and .b #0x000f ,r14 push.w #0x000e
R0 R0 R0
0=word, 1=byte DR=R0, indirect, auto-inc mode push instruction (immediate)

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Quiz 5.6 (solution)

R0 R0 R0
1000 0011 1 0 01 0001
sub.w #1 ,0(r1)
sub instruction 0=word, 1=byte DR=R1, indexed mode SR=R3,register Constant 1

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Quiz 5.6 (solution)

1000 0011 1 0 01 0001

0010 00 1111111101
sub.w #1 ,0(r1)
jne 0x8026
R0 R0
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jne instruction (-3 x 2) + 0x802c
69
Quiz 5.6 (solution)

0100 0000 0 0 11 0001 0100 0000 1 0 11 0010 0100 0011 0 0 00 1110 0101 0011 0 1 01 1110 1111 0000 0 1 11 1110 000100100 0 11 0000 1000 0011 1 0 01 0001 001000 1111111101 0100 0001 0 0 11 1111 mov.w #0x0600,r1 mov.w #0x5a1e,&0x0120 mov.w #0,r14 add.b #1,r14 and.b #0x0f,r14 push sub.w #0x000e #1,0(r1)
jne 0x8026 mov.w @r1+,r15

70
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BYU CS/ECEn 124
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Chapter 05 - Msp430 Isa

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Chapter 05 - Msp430 Isa

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Chapter 5 MSP430 ISA The Instruction Set

BYU CS/ECEn 124

High-level language statements

Assembly language instructions

Machine language instructions

Problem solved by Algorithm

One algorithm = Many statements Chapter 05 - MSP430 ISA

One statement = Many instructions

Instruction = Many cycles 3

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Instruction Set Architecture

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RISC/CISC machine 27 orthogonal instructions

8 jump instructions 7 single operand instructions 12 double operand instructions

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