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3/26/2013
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3/26/2013
ADC TEST
Mixed Signal VLSI
Xunyu Zhu

Dr. Chris Hutchens
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3/26/2013
ADC TEST
Test methods
1. Static test - SIN Histogram
i.e. Gain and Offset
2. Dynamic test
i.e. ENOB using 16K FFT
SIN fit.
Outline
Does this make sense??
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ADC TEST
Static Tests
Number of digitized bits
Gain
Offset
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Monotonicity

Test Specification
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ADC TEST
Dynamic Tests
Effective number of bits (ENOB)
Signal-to-noise ration (SNR)
Total Harmonic distortion (THD)
Total spurious distortion (TSD)
Spurious-free dynamic range (SFDR)
Test Specification
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ADC TEST
Objective:
Converter accuracy
Transfer function of the converter
Monotonicity of the converter
Quantify the gain, offset, DNL and INL of the
converter

Disadvantage:
Nonlinearites which coupled to the input signal
bandwidth cannot be revealed
For high bit converters, measurement is lengthy
Static Test
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ADC TEST
Test Setup
Clock
Analog
Digital
Digital
Digital Control
Ramp???? test setup
Each voltage step less or equal to 1/8 LSB
At lest 10 samples sampled at each voltage level
Logic Analyzer -
Word length > N
Word depth > > 20*2
N


Pattern generator -
Period jitter (peak to peak)
less than
1
2 2
1
+

N
B f t
f
B
is the input signal
frequency
N is the ADC resolution
Source generator-
Resolution N +3 bits
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ADC TEST
Static Test
ADC static test result
G is the Gain
V
os
is the offset
T
1
is the ideal value corresponding to T[1]
T[k] is the input value
Q is the ideal width of a code bin
[k] is the residual error
Transfer function described as below
Using conventional linear least-squares estimation
techniques, get G and V
os
as below
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ADC TEST
Differential nonlinearity
Static Test
Too Many fonts
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ADC TEST
Static Test
Illustration of DNL and INL
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ADC TEST
Static Test
Integral nonlinearity
Q is the ideal code bin width, expressed in input units,
V
FS
is the full-scale range of the ADC in input units.

The maximum INL is the maximum value of |INL[k]| for all k.
Where
INL(k) is the integral nonlinearity at output code k,
[k] is the difference between ideal output bin T[k] and T[k] computed from G and Vos,
that is,
os
V k T G T k Q k T k T k + = = ] [ ) 1 ( ] [ ] [ ' ] [
1
c
Too many different fonts
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ADC TEST
Objective- Measure
Harmonic and spurious distortion information
Input bandwidth
Signal-to-noise ratio
Effective number of bits (ENOB)
Spurious-free dynamic range (SFDR)
Dynamic Test
Think about the consistency with slide 4
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ADC TEST
Disadvantage
Cannot test for monotonicity of the ADC
Input signal must be sampled using an integer
number of cycles
Histogram test measure the noise of the ADC
Test methods
Histogram test
FFT test

Dynamic Test
What is the recommended method for measuring the noise of an ADC?
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ADC TEST
Test setup for histogram and FFT test
Dynamic Test
Clock
Analog
Digital
Digital
Logic Analyzer -
Word length > N
Word depth > 2*2
N ???


Pattern generator -
Period jitter (peak to peak)
less than
1
2 2
1
+

N
B f t
f
B
is the input signal frequency
N is the ADC resolution
Source generator-
Resolution N +3 bits
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ADC TEST
Record length selection
There must be an exact integer number of cycles in a
record, and the number of cycles in a record must
be relatively prime to the number of samples in the
record.

s i
f
M
J
f =
f
i
is the input signal frequency
f
s
is the sampling signal frequency
J is the number of cycles per record
M is a record length
Histogram Test
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ADC TEST

The procedure to find the near-optimum input signal frequency

a) Find an integer, r, such that the desired frequency is approximately
f
s
/r.
b) Let J equal the number of full cycles that can be recorded at the
frequency in step a)
J=int(M/r)
c) Let f
i
equal

1
i

=
rJ
Jf
f
s
Histogram Test cont
a) b) etc are
NOT consistent
with the rest of
the ppt slides
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ADC TEST
Histogram Test cont
Illustration of histogram test results
Review SIN
reconstruction
after this slide
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ADC TEST
Total harmonic distortion
The THD is also often expressed as a dB ratio with respect to rms amplitude of the
fundamental component of the output,
FFT Test
bandwidth full in frequency al funderment the of
mirror of magnitude averaged the is f f X
frequency al funderment the of magnitude averaged the is f X
f f X f X A
A
THD
THD
i s avm
i avm
i s avm i avm rms
rms
dB
) (
) (
)) ( ( )) ( (
2
1
) ( log 20
2 2
10

+ =
=
Too
Many
Fonts
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ADC TEST
FFT Test
Total spurious distortion
Each of the spurious frequencies in f
sp
is the
frequency of a persistent spectral output component
that is neither the fundamental nor a harmonic
distortion component.
( )
samples of number the is M
distortion spurious the is f
f X
M
TSD
sp
n
n sp avm
= ) (
1
] [
Too
Many
Fonts
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ADC TEST
FFT Test
Spurious-free dynamic range (SFDR)

The ratio of the amplitude of the ADC output averaged spectral
component at the input frequency, f
i
, to the amplitude of the largest harmonic
or spurious spectral component observed over the full Nyquist band:
)
} ) ( ) ( { max
) (
( log 20 ) (
,
10
h avg s avg
f f
i avg
f X or f X
f X
dB SFDR
h s
=
Where
X
avg
is the averaged spectrum of the ADC output,
f
i
is the input signal frequency,
f
s
and f
h
are the frequencies of the set of harmonic and
spurious spectral components
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ADC TEST
FFT Test
Spectrum of a sine wave and its harmonics
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ADC TEST
FFT Test
Spectrum of a real ADC FFT test result
Fundamental
frequency
Harmonics
Spurious frequency
SFDR
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ADC TEST
SINAD is the ration of the signal to the total noise
Time domain calculation
noise rms
signal rms
SINAD
given is SINAD ratio distortion and noise to signal The
wave e f it best the of set data the is y
set data sample the is y
where
y y
M
noise rms
n
n
M
n
n n
=


(

=

=
) (
sin
) (
1
'
2 / 1
1
2 '
Signal-to-noise and distortion ratio (SINAD)
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ADC TEST
Frequency domain calculation
2 / 1
1
0
2
2 2
) (
1
)) ( ( )) ( (
1
(

=
+ =

=
M
m
m avm
i s avm i avm
f E
M
noise rms
f f X f X
M
signal rms
Effective number of bits (ENOB)
)
) 2 / (
( log ) 5 . 1 ( log
2
1
) ( log
2 2 2
V
A
SINAD ENOB =
Where
A is the amplitude of the sine wave fitted to the output
V is the full-scale range of the ADC under test
Signal-to-noise and distortion ratio (SINAD) cont
Summary Must follow