Congestion Driven Placement for VLSI Standard Cell Design

Shawki Areibi and Zhen Yang School of Engineering, University of Guelph, Ontario, Canada
December 2003 (sareibi@uoguelph.ca, zyang@uoguelph.ca)

ICM 2003, Cairo

Outline
Introduction

Background
Motivation

Congestion Optimization

Experimental Results
Summary & Conclusions
ICM 2003, Cairo

Introduction
The interconnect has become a critical determiner of circuit performance in the deep sub-micron regime. Circuit placement is starting to play an important role in todays high performance chip designs. In addition to wire length optimization, the issue of reducing excessive congestion in local regions such that the router can finish the routing successfully is becoming another important problem.
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VLSI Design
Specification Architectural design

Physical Design
Partitioning

Logic design
Circuit design Physical design

Placement

Routing Test/Fabrication

Layout Style

Layout Styles

Full Custom

Semi Custom Cell-Based ArrayBased

Standard Cell

Macro Cell

Gate Array

FPGA

Standard Cell Layout Style

Feature:
Row based layout
Standard cells Routing channel
Routing Channel Feedthrough Standard cell I/O Pads

Advantages:
High productivity More efficient space Well-suited for automated design

Circuit Layout - Partitioning

Task Partition circuit into several sub-circuits.

Objectives
Make the size of each component within prescribed ranges Minimize the number of connections between the components.
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Circuit Layout - Placement

In1 In2 In3 In4 In5 In6 In7 In8

1 5
In2

In1

In3

1 7 3
In6

5 8 6

In 4 Out1

2
7 3 6 4

Out1

In5

4
In8

In7

Minimize the total estimated wire length of all the nets.

Minimize the interconnect congestion.

Circuit Layout

Global Routing

Objectives
Minimize the total wire length and critical path delay.
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Circuit Layout
Determine the location of modules. Connect the modules inside the boundary of a VLSI chip. Typical Objectives Minimize the chip area Minimize the interconnect delay
W O R L D H E L L O

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Why Is Placement Important?

The circuit delay, power dissipation and area

are dominated by the interconnections.

- Circuit Placement becomes very critical in
Delay (ns0 1.0

todays high performance VLSI design. Interconnect

delay

The first phase in the VLSI design that

determines the physical layout of a chip. Gate delay - The quality of the attainable routing is 0.1 1.0um 0.5um 0.25um highly determined by the placement.
Minimum Feature Size

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Placement Techniques
Placement Algorithms Constructive Placement

Iterative Improvemen t Simulated Annealin g

Cluster Growth Technique

Numerical Optimizatio n

Genetic Placement

Partitioning Placement

Force-directed Placement

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Traditional Placement Approach

Circuit Generated From Logical Description

Initial (global) Placement by Constructive Algorithms

Produce

a good initial placement in reasonable time

Improve (detailed) Placement by Iterative Algorithms

Produce

a good final

placement

Valid Coordinates for each cell

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Multi-Level Clustering
1. Bottom-up procedure (clustering) 2. Top-down procedure (de-clustering)
clusters formed from cells in previous level Level n . . . . Level 1 initial placement iterative improvement

cluster

de-cluster a simple interchange heuristic

cluster Level 0 (Flat) a high quality solution

de-cluster

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Traditional Methods: Drawbacks

May lead to routing detours around the

regions ( i.e. larger routed wire length).

May create an unroutable placement( i.e

leads to replacement and repartitioning).

Congestion reduction in placement stage

would be more effective.

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Congestion
Global Bin Global Bin Edge

Overflow on each edge = Routing Demand - Routing Supply 0 (otherwise)

Total Overflow = overflow all edges Routing demand = 3 Assume routing supply is 1, overflow = 3 - 1 = 2 .

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Congestion Reduction Techniques

Congestion Reduction

Integrated Technique

Post-processing Technique

Quadratic Placment

Simulated Annealing

Congestion Reduction During Placment

Partitioning Based Placement

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Congestion Optimization
Module Description & Netlist Routing Estimation Congested Region Identification Congested Region Expanding

Initial Placement

Iterative Improvement

Congestion Reduction

Congestion Reduction Valid Coordinates for each cell

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Routing Estimation
Bounding Box Routing Estimation.

Based on the probability of having a wire within a global bin covered by the bounding box of net K:
bin(0,2)

For each yellow bin, the Horizontal Routing Demand of net K is:1/3 Total Horizontal Routing Demand of net K :2

Net K
bin(0,0) bin(2,0)

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Congestion Cost Function

Cost =

S Routing Demand +( S Overflow)2

Wire length Overflow

Total Bounding Box Based Wire length: 4

Horizontal Routing Demand: 2 Vertical Routing Demand: 2

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Identifying Congested Regions

A global bin is congested if one of its four global edges is congested. A maximum number of congested bins in one congested region is set to prevent forming too large congested regions.
Bin(i,j)
Congested Reg_3 Congested Reg_2 Congested Reg_1
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Neighborhood bins

Congested Region Expansion

For a single congested region, the larger the expansion area is, the better the optimization result can be obtained. However, the expansions of multiple congested regions may lead to new congested regions.
Original Congested Region Expansion Area

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Test Circuits
Circuit Fract cells 125 Pads 24 Nets 147 Pins 876 Rows 6

Small

Prim1
Struct Ind1

752
1888 2271 2907 6417

81
64 814 107 97

904
1920 2478 3029 5742

5526
5471 8513 18407 26947

16
21 16 28 46

Medium

Prim2 Bio

Ind2

12142
21854 25114

495
64 64

13419
22124 25384

125555
82601 82751

72
80 86

Large

Avq.s Avq.l

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Experimental Results
Test Circuit Statistics (for flat approach)
Circuit Fract Prim1 Struct Ind1 Prim2 Bio Ind2 Ind3 Avq.s Avq.l cells 125 752 1888 2271 2907 6417 12142 15059 21854 25114 Nets 147 904 1920 2478 3029 5742 13419 21940 22124 25384 Grids 6x9 16x21 21x32 15x54 28x49 46x60 72x76 54x111 80x114 86x120 #c/bin 2.3 2.2 2.8 2.8 2.1 2.3 2.2 2.5 2.4 2.2 V/H Cap 6/6 11/10 8/7 19/7 16/13 11/10 17/20 27/20 12/10 12/10
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Congestion Reduction (at flat level)

Congestion Comparison 450 400 350 300 250 200 150 100 50 0
Wirelength Comparison

2.5E+07 2.0E+07 1.5E+07 1.0E+07 5.0E+06

Ind1 Prim2 Bio Ind2 Avq.s Avq.l

0.0E+00

Ind1 Prim2

Bio

Ind2 Avq.s Avq.l

Without congestoin reduction With-congestion reduction

Without congestoin reduction With-congestion reduction

Average Congestion imp: 51% Average Wire length Increase: 3% Average CPU Time Increase: 30%
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Congestion Reduction (at level-3)

Congestion Comparison Wirelength Comparison
2.5E+07 2.0E+07 1.5E+07 1.0E+07 5.0E+06 0.0E+00

4000 3500 3000 2500 2000 1500 1000 500 0

Ind1

Prim2

Bio

Ind2

Avq.s

Avq.l

Ind1

Prim2

Bio

Ind2

Avq.s

Avq.l

Without congestoin reduction With-congestion reduction

Without congestoin reduction With-congestion reduction

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Results Analysis
Incorporating a post processing technique into the hierarchical placement may not be an effective way to reduce the congestion due to the interplay between the wire length placement algorithm and congestion reduction technique. The wire length minimization should be performed on clustering levels, while the congestion optimization should be only turned on at the flat level.

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Congestion Reduction (after hierarchy)

Congestion Comparison 3500 3000 2500 2000 1500 1000 500 0
Ind1 Prim2 Bio Ind2 Avq.s Avq.l

Wirelength Comparison

2.5E+07 2.0E+07 1.5E+07 1.0E+07 5.0E+06 0.0E+00

Ind1 Prim2 Bio Ind2 Avq.s Avq.l

Without congestoin reduction With-congestion reduction

Without congestoin reduction With-congestion reduction

Average Congestion imp:37% Average Wire length Increase: 3%

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Conclusions and Summary

A post-processing congestion reduction technique is implemented and incorporated into the flat and

hierarchical placement.
A post-processing technique can reduce the congestion of flat placement largely by 51% on average with a slight increase of wire length. For hierarchical congestion-driven placement, it seems to be more beneficial to incorporate the congestion reduction phase at the flat level rather than within the levels of

hierarchy.
The congestion improvement achieved by performing congestion optimization at the flat level is 37% on average.
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Congestion Driven Placement

A B C D

Shorter Wire length Channel Density: 3 (track: 3)

(channel capacities:2) Unroutable Layout Longer Wire length Channel Density: 2 (track: 2)

H
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