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CPU R W 0 . . . . . . . . . . . . . . . .
15 .. . . .. . . .. . . . . . . .
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C O N T R O L B U S
2
Data Bus
Address
The Address at which the operation is to be performed, is generated by the CPU This address is passed on the Address bus And is temporarily stored in Memory Address Register Memory Address Register selects one and only 1 Address at a time.
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Address
Address Bus 3 RAM
3 CPU R W 0 . . . . . . . . . . . . . . . .
15 .. . . .. . . .. . . . . . . .
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C O N T R O L B U S
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Data Bus
Control Signal
The CPU generates 2 control signals for memory operations
Read Write Read 0 0 1 1 Write 0 Neither Reading nor Writing Memory 1 Write into Memory 0 Read from Memory 1 Illegal operation (not-defined)
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Control Signal R= 1
Address Bus 3 RAM
3 CPU R W 0 . . . . . . . . . . . . . . . . 1
15 .. . . .. . . .. . . . . . . .
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C O N T R O L B U S
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Data Bus
Data
The Direction of data flow depends on the control signal generated by the CPU. Read = 1 and Write = 0
The Data will move from RAM to CPU
3 CPU R W 0 . . . . . . 0. . . . . . . . . . 0
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15 .. .. .. 1 . 1 . . . .
. . . . . . . . . 1 0 0
C O N T R O L B U S
. 1 . 1. 0. 1
Data Bus
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3 CPU R W 1C O N T R O L
15 .. .. .. 1 . 1 . . . .
. . . . . . . . . 1 0 0
0 . . . . . . 0. . . . . . . . . . 1
. 0 . 1. 1. 1 1
B U S
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Data Bus
3 CPU R W 1C O N T R O L
15 .. .. .. 1 . 0 . . . .
. . . . . . . . . 1 1 1
0 . . . . . . 1. . . . . . . . . . 1
. 0 . 1. 1. 1 1
B U S
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Data Bus
The CPU
The CPU is the brain of the computer.
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14
16
Decode
Fetch
Execute
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2) Decode:
Decode the bit pattern in the instruction register.
3) Execute:
Perform the action requested by the instruction in the instruction register.
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Instruction Register
Fetched instruction is placed in the instruction register Types of instructions
Processor-memory
transfer data between processor and memory Read Register2, OxAA2
Processor-I/O
data transferred to or from a peripheral device cin, cout
Data processing
arithmetic or logic operation on data Add Register2,Register3,Register1
Control
alter sequence of execution Jump 0xFF3
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