Saha

S. Saha and B.
Gadepally
Technology CAD: Technology
Modeling, Device Design and
Simulation

S. Saha and B. Gadepally
2004 VLSI Design Tutorial, January 5, 2004
Mumbai, India
Coordinator: Prof. Bhaskar Gadepally
Adjunct Prof., Electrical Engineering, IIT Bombay
Chairman, Reliance Software Consulting, Inc.
155 E. Campbell Ave., Campbell, CA 95008 (USA)
bhaskar@relianceworld.com

Mumbai, India
Simulation
Instructor: Dr. Samar Saha
Silicon Storage Technology, Inc.
1171 Sonora Court
Sunnyvale, CA 94086 (USA)
samar@ieee.org

Mumbai, India
Simulation
Mumbai, India S. Saha and B. Gadepally 4
Tutorial Outline
Prof. B. Gadepally:
Introduction and Tutorial Overview.
Dr. S. Saha:
Front-end Process Technology CAD (TCAD) Models and
Process Simulations
Device TCAD Models and Device Simulations
Industrial Application of TCAD
+Calibration of Process and Device Models
Industrial Application of TCAD in
+Device Research
+Compact / SPICE Modeling.
Bhaskar Gadepally
Technology CAD: Technology Modeling,
Device Design and Simulation

Introduction and Tutorial Overview
Mumbai, India
Mumbai, India Bhaskar Gadepally 6
Overview of IC Technology
In the past three decades:
device densities have grown exponentially
device and technology complexities have increased
significantly
design constraints are many-fold:
+ultra thin oxide
+interconnect
+power supply
technology development cost has increased enormously.
Overview of IC Technology
Channel Engineering
- non-uniform channel doping
- Quantum Mechanical effects
- low-diffusivity impurities
- threshold voltage control
Source-Drain Engineering
- ultra-shallow extensions
- low-energy implants
- RTA/LTA techniques
- halo optimization
p-substrate
p-well n-well
n+
PMOS
n+ p+ p+
STI
Halo
P+ poly
Spacer
NMOS
STI
(Shallow
Trench
Isolation)
Gate Engineering: Dielectric
- ultra-thin gate oxide
- direct tunneling
- high-k dielectrics
Gate Engineering: Stack
- dual-poly / poly depletion
- work function engineering
- interface properties
N+ poly
Overview of IC Devices
New device and device physics are continuously
evolving:
nano-scale devices
microscopic diffusion
quantum mechanical carrier transport
molecular dynamics
quantum chemistry
high-frequency interconnect behavior.
Technology CAD
With the increased complexities in IC process and
device physics:
intuitive analysis is no longer possible to design
advanced IC processes and devices
TCAD tools are crucial for efficient technology and
device design
+to quantify potential roadblocks
+to indicate new solutions
+for continuos scaling of devices.

Technology CAD
Scope of TCAD:
front-end process modeling and simulation
+implant, diffusion, oxidation etc.
numerical device modeling and simulation
+I - V, C - V etc. simulation
topography modeling and simulation
+deposition, lithography, etching etc.
device modeling for circuit simulation
+compact / SPICE modeling
interconnect simulation
+capacitance, inductance etc.
Tutorial Objective
Offer insight into the physical basis of TCAD,
especially, bulk-process and device TCAD.
Describe systematic methodologies for an effective
application of TCAD tools.
Describe systematic calibration methodology for
predictive usage of TCAD tools:
process models
device models.
Offer users sufficient insight to leverage new tools.
Session 1: Bulk-Process Simulation
Front-end process models implemented in process
TCAD tools:
ion implantation models
+analytical
+Monte Carlo
microscopic diffusion models
+point defects
oxidation
+transient enhanced diffusion.
Session 2: Device Simulation
Device models implemented in device TCAD tools:
fundamentals of carrier transport
+drift-diffusion solution
+hydrodynamic solution
+carrier mobility models
device physics of nanoscale technology
+inversion layer quantization
fundamental limits of MOSFETs.

Session 3: Industry Application
Introduction to process and device simulation tools.
Mesh generation.
Model selection.
Predictive usage of TCAD:
process model calibration
device model calibration.
Predictive simulation of CMOS technology.
Session 3: Industry Application - Calibration
Calibration Effort
T
D

E
f
f
e
c
t
i
v
e
n
e
s
s

Low Moderate High
L
o
w

M
o
d
e
r
a
t
e

H
i
g
h

No or a limited
calibration only
provides some
physical trends
and is useful
for a first-order
process and
device analysis.
Global calibration
provides higher
accuracy and
predictability of
simulation data.
Local calibration
with the previous
generation of
technology will
provide physical
trends. Absolute
values may not
match real data.
Session 4: TCAD in Research & Modeling
Simulation tools in device research:
simulation structure
model selection
examples
+sub-100 nm MOSFETs
+DG-MOSFETs - FinFETs.
TCAD in device (compact) modeling:
examples
+substrate current model
+flash memory cell macro-model.
Samar Saha

Bulk-Process Simulation
Mumbai, India
Mumbai, India Samar Saha 18
Outline
Introduction.
Bulk-process Models:
Ion Implantation
Diffusion
Oxidation.
Summary.
Introduction
Front-end IC fabrication processes include:
implant: S/D and halo (low energy); well (high energy) etc.
diffusion: Rapid thermal annealing (RTA) Transient
Enhanced Diffusion (TED) and other anomalous effects
oxidation: gate oxide, STI liner oxide etc.
p-substrate
p-well n-well
n+
PMOS
n+ p+ p+
STI
Gate oxide
Halo
P+ poly Spacer
N+ poly
NMOS
STI
(Shallow
Trench
Isolation)
Source Source Drain Drain
Introduction
Objective of this session:
understanding of physical models implemented in a
process TCAD tool
+model hierarchy
+model limitations
+building new models
basic understanding of general purpose simulator
internals
TCAD models in general without considering any
particular tools.
Ion Implantation
Ion Implantation Mechanisms.
Ion Implant Models:
Analytical
Monte Carlo (MC).
Implant-induced Damage Modeling.
Plus-one Approximation.
Summary.
Ion Implantation
Bombard wafers with
energetic ions energy, E
0.5 KeV - 1 MeV > E
binding
.
Ions collide elastically with
target atoms creating:
ion deflections, energy loss
displaced target atoms
(recoils).
Ions suffer inelastic drag
force from target electrons
ion energy loss
lattice heating.
Ion
Target
R
e
c
o
i
l

Ion Implantation
Channeling is caused by
ions traveling with few
collisions and little drag
along certain crystal
directions.
Ions come to rest after
losing all the energy on:
elastic collisions (nuclear
stopping)
inelastic drag (electronic
stopping).
Ion
Target
R
e
c
o
i
l

Ion Energy Loss Mechanisms
Nuclear stopping (S
n
(E)):
ion energy loss to target
atom by interaction with
the electric field of the
target atoms nucleus
classical relationship of two colliding particles
the scattering potential with the exponential screening
function is given by

where
Z
1
= atomic number of incoming ion
Z
2
= atomic number of target atom.
e
a
r
i
b
a
r V
i
=
r 4
Z Z
q
) (
1 2
2
tc
Ion
u
Ion Energy Loss Mechanisms
Electronic stopping (S
e
(E)) is due to the viscous drag
force on moving ion in a dielectric medium.
( ) E Z Z
k
S
e
e
,... ,
2 1
=
k
e
is a model parameter.
Accurate model must
account for the variation
of S
e
in space.
Stopping power S of an
ion is given by:
electronic nuclear
dx
dE
dx
dE
S
|
.
|
\
|
+
|
.
|
\
|
=
Ion Range Distribution
Ions come to rest over a distribution of locations.
Peak, depth, and lateral spread of distribution are
determined by:
ion mass, energy, dose, and incident angle
target atom, composition, geometry, structure, and
temperature.
Implanted profile can be represented by:
particles
distribution functions.
The as-implanted 1D
distribution function is
described by a series
of coefficients called
moments.
2D distribution of the
implanted profile is
constructed from 1D
distribution function
taking lateral spread
~ vertical spread.
1D Analytical Ion Implantation Models
Gaussian distribution:
amorphous targets
two coefficients

where
Q = implant dose (#/cm
-2
)
R
p
= projected range normalized first moment
o
p
= straggle/standard deviation second moment.
( )
(
(
=
o
o t
2
2
2
exp
2
) (
p
p
p
R x
Q
x N
x
R
p

N
Pearson-IV:
crystalline targets without channeling
+four coefficients (R
p
, o
p
, skewness, kurtosis)
crystalline targets with channeling, tilt, and rotation.
+six coefficients.
Dual Pearson-IV:
crystalline targets with channeling, tilt, and rotation
second profile to model the channeling
nine coefficients.
Legendre Polynomials - 19 coefficients.
Coefficients are fit to the measured doping profiles.
Coefficient-set for each distribution is tabulated for
different:
ion mass (As, B, In, P, Sb)
dose, energy, tilt, and rotation
target type.
Multi-layer targets:
each material is treated separately and scaled by its R
p
.
dose absorbed on the top layer is calculated and is used
as the dose matching thickness for the layer below.
2D/3D Analytical Ion Implantation Models
Each 1D profile along a vertical line is converted to
2D or 3D distribution by multiplying it by a function of
lateral coordinates:

here lateral straggle, o
l
~ o
p

Multi-layer targets and sloped surfaces are
converted to 2D/3D by dose matching approach.
More complex models have o
l
(x).
Low energy profiles need non-separable point-
response functions.
l
l
y
x N y x N
o t
o
2
2
exp
) ( ) , (
2
1
|
|
.
|
\
|
=
Monte Carlo Modeling of Ion Implantation
The collision energy loss is modeled by binary
collision approximation (BCA), that is, each ion
collides with one target atom at a time.
The energy loss (AE) is modeled in terms of:
incident energy, E
0
and scattering angle, u
0
of ion
separation between two particles
coulomb potential between two particles
impact parameter.
BCA requires special formulation for:
ion channeling
low energies when lattice movements come into play.
Monte Carlo Modeling of Ion Implantation
Ongoing development in MC modeling is to improve:
speed of calculations
electronic stopping power, S
e
model
+detailed local model for S
e

+local and non-local split in energy loss due to S
e

where
f
nl
= fraction of non-local energy split
a = universal screening length
p = impact parameter.
Overall accuracy of MC implant model is excellent.
e
nl
nl
S
a
p
a
f
NL f E
|
|
.
|
\
|
|
.
|
\
|
+ = A exp
2
1
2
t
Ion Channeling in Crystalline Silicon
Along certain angles in crystal, ion may encounter
no target atoms.
Ion
Repeated small-angle
collisions steer the ion
back into the channel.
Channeling was first discovered by MC simulation.
Channeling is:
important at any energy
critical at low energy where <110> channels steer Boron
ions under MOS gate.
Analytic channeling model is complex.
Ion Channeling in Crystalline Silicon
Damage Creation Models
Each incoming ions generates damage seen by
subsequent ions:
recoils target atoms knocked out of lattice sites
amorphous pockets.
The effect of damage is significant on as-implanted
profile as well as during subsequent diffusion.
Models based on Kinchin-Pease formulation is used
to estimate damage density: n = E
r
/2E
d
where
E
r
= recoil energy
E
d
= target displacement energy (~ 15 eV for Silicon).
Plus-one Damage Model
Most recoiled interstitials (I) find a vacancy (V) and
recombine rapidly either during the implantation or
the first instants of annealing.
Distribution of remaining recoils shows:
net excess of V near the surface
net excess of I toward bulk.
At low ion mass and/or moderate energy:
population of net I and net V is less than the population
of I due to dopant atoms taking substitutional sites
one extra-ion is created for each dopant atom taking a
substitutional site.
Deviation from Plus-one Model
Plus-one approximation often fails for:
heavy ions
+as the population of recoils can become quite large
relative to extra ion population
low energy
low dose.
An effective plus-n factor as a function of ion
species, energy, and dose is used. Typical values:
As: n ~ 3.5 @ E ~ 5 KeV; n ~ 1.2 @ E ~ 500 KeV
B: n ~ 1.2 @ E ~ 5 KeV; n ~ 1.0 for E > 20 KeV
P: n ~ 2.2 @ E ~ 5 KeV; n ~ 1.0 @ E ~ 500 KeV.
Ion Implantation: Summary
Ion implantation with ion energy > E
binding
of target
atoms is used to implant impurity atoms into target.
Analytical ion implantation model:
the impurity profile is represented by moments for
different species, dose, energy, tilt, and rotation
the moments are extracted from the experimental profile
to create look-up table
simulation is performed using this look-up table.
MC ion implantation model is more accurate,
particularly for low energy.
The implant damage is modeled by plus-n model.
Diffusion
Fundamentals of Dopant Diffusion
Ficks Laws
Oxidation Enhanced Diffusion (OED)
Oxidation Retarded Diffusion (ORD)
Transient Enhanced Diffusion (TED).
Point Defect Model.
Clusters and Precipitates.
Polysilicon Diffusion.
Impurity Profiling.
Summary.
Ficks Laws of Diffusion
Ficks first law:
describes flux (F) through any surface
diffusion is downhill - high low concentration, - sign

Ficks second law law of conservation of particles

Low concentration diffusion in
silicon is Fickian - each dopant
A satisfies:
C D
x
C
D F V =
A
A
=
F
t
C
. V =
c
c
( ) A
D
t
C
A
A
V V =
c
c
0
.
F
in
F
out

Ax
AC
(D diffusivity = constant)
Concentration-Dependent Diffusion
Typically, intrinsic carrier concentrations (n
i
) at
processing temperatures are high ~ 10
19
cm
-3
.
For high doping concentrations, C > n
i
, dopant
diffusion shows enhancements of the form:

Diffusion enhancement is due to the variation of
point defect population with Fermi level.
The effective extrinsic diffusivity is given by:
|
|
.
|
\
|
+
|
|
.
|
\
|
+
|
|
.
|
\
|
+ =
i i i
n
p
c
n
n
b
n
n
a
D
D
2
0
1
;
2
|
|
.
|
\
|
+
|
|
.
|
\
|
+
|
|
.
|
\
|
+ =
i
mm
i
m
i
p x
n
n
D
n
n
D
n
p
D D D
mm m p x
o
D D D D D
where
+ + + =
Surface Effects on Bulk Diffusion: OED/ORD
Experimental data show that processes which
modify the surface can affect diffusion in the bulk.

Enhancement of diffusivity in one species while
retardation in another is the evidence of two different
diffusion mechanisms I and V.
Diffusion process Species /
defects Oxidation Oxinitridation Nitridation
B, P, I Enhanced Enhanced Retarded
As Enhanced Enhanced Enhanced
Sb
Enhanced
then retarded
Enhanced
then retarded
Enhanced
Stacking
Faults
Grow Grow Shrink
Transient Enhanced Diffusion (TED)
Anomalous displacement of implanted dopants during
low temperature anneals.
Reverse temperature effect: displacement larger at
lower temperatures - up to 0.3-0.4 m.
Displacement increases with implant dose and energy.
Corresponds to temporary increase in diffusivity ~
10,000X.
Implant of one species can drive diffusion of another.
Enhancement is transient.
Spatially non-uniform diffusion enhancements.
Reduced activation.
Transient Enhanced Diffusion (TED)
As implanted over a
buried B layer.
As implant creates
damage deep into
the substrate.
The implant damage
causes a significant
enhancement in B
diffusion deep into
the substrate during
20 sec. anneal at
850 C.
Simulation results
Point Defect Model for Dopant Diffusion
Point defects (I and V) model explains:
most of the observed trends in dopant diffusion by
relating them to the properties of I and V
action-at-a-distance effect of the surface on bulk
diffusion.
Vacancy mechanism
As, Sb
Kick-out mechanism
B, P, In, As, Au, Zn, P
above 900 C
Frank-Turnbull
mechanism
Zn, below 900 C
Defect Charge States
Defects which have states in the gap will have a
distribution of charge states.
The concentration of charged point defects depends
on Fermi level.
Dopants can diffuse with any of the defect charge
states, some combinations have higher probability.
In principle, must solve a set of:
PDEs one for each combination.
Five-stream diffusion model solves equations:

Three-stream model solves equations.
+ +
e ch defect dopant
N N N
arg
e ch defect dopant
N N N
arg
e ch dopant defect dopant
N N N N
arg
+ +
defect dopant
N N +
Electric-field Effects
For high doping
concentration > n
i

at the processing
temperature, the
electric field set up
by ionized dopants
affects diffusivity.
Example:
As + B co-diffusion
at 900 C, 15 min.
B- pulled towards
the N+ region due to
e-field effects.
Generation/Recombination of Defects
General flux model:
where u= fraction of silicon atom injected

V
m
= silicon atom/cm
3

assumed generation growth rate, G.
recombination rate surface excess I - I* and increases
under a growing surface.
Lateral diffusion of defects during OED is governed
by the ratio of D
I
/K
inert
~ 10 m.
rec gen surf
F F F =
). ( ) ( 1
,
* *
0
0
I I K I I
G
G
K K F
G
G
G V F
total
k
r inert rec
g
m gen
=
(
(
+
|
|
.
|
\
|
=
|
|
.
|
\
|
=u
Surface Generation/Recombination
During OED, recombination/generation fluxes are
large and must balance:

Fixed interstitial super-saturations, also, occur under
nitride, silicide surfaces.
During TED, recombination appears to be fast, even
at inert surfaces, recombination rate:
Several models are available.
Optimize K
inert
for TED and adjust u to fit OED at the
expense of lateral OED decay length.
total
gen
K
F
I I + =
*
. 1 . 0 m K D
inert I
<
Gradient Effects in Transient Diffusion
Dopant flux arises from diffusion of defects-dopant
pairs:
boron flux = D
BI
V[BI].
Number of pairs is proportional to the boron and
interstitial concentrations:
boron flux = D
BI
k
pair
(IVB + BVI)
where
IVB = interstitials enhance boron diffusion
VI = boron diffusion due to defect gradient
During TED, VI is large near the surface causing:
extra dopant flux to the surface
surface pile-up (and possible interface loss) of dopant.
Interstitial Clustering Model
The growth and dissolution is given by:

where
k
d
is the decay constant
k
c
is the growth constant
C = concentration of clustered interstitials
I = concentration of unclustered interstitials.
After implantation I is large, oC/ot = C(k
c
I) clusters
grow exponentially until I = k
d
/k
c
.
When I is small, clusters decay exponentially with
time constant 1/k
d
.
CI k C k
t
C
c d
+ =
c
c
{311} Cluster Dissolution
{311} defects:
rod-shaped defect clusters condensed from +1 amount
of damaged silicon-I at annealing T > 400 C
precipitate on {311} planes and extend in the <110>
directions to form planar defects.
Time scale for {311} evaporation is similar to the time
scale for TED.
Simple reaction-based model offers first-order
account of evaporation curve.
Steady super saturation of dopant diffusion is
observed during TED.
Dopant Clustering/Precipitation
Dopants are only soluble up to a limit at any
temperature (solid solubility limit).
Dopants also show deactivation below the solid
solubility limit.
Due to the clusters of size
m dopant atoms such as
As with m = 4,
clustering reaction emits
interstitials to generate required V.
Can generate enhanced diffusion at the same level
as TED.
As
V
As
As
As
Chemical Pump Effects
Dopant atom A interacting with I form A + I AI
interstitial-assisted mobile species.
When AI pairs diffuse out of a region of high I* to a
region of low I*, pairs are out of equilibrium and must
dissociate, AI A + I.
A is deposited while I diffuses (pumped) away from
the surface enhancing diffusion in bulk.
Surface dopant layer may cause enhanced diffusion
in bulk - e.g. D/D* = 70 at 900 C.
Causes cooperative diffusion, e.g. emitter push
effect in bipolar junction transistors.
Diffusion in Polysilicon
Point defects usually pinned near equilibrium in poly
due to grain boundaries.
Dopants diffuse in two streams via grain and in
boundary.
An effective model includes:
two streams
dopant transfer from grain to grain boundary
grain growth with time
dopant transfer to grain boundary.
Segregation coefficient, growth rate, and re-growth
rate = f(temperature, grain size, Fermi level).
Metrology for Developing Diffusion Models
Spreading resistance
profile (SRP)
1D carrier
profiles
good sensitivity
modest depth
resolution
carrier spilling
difficult to use
for shallow
junctions.
1.E+15
1.E+16
1.E+17
1.E+18
1.E+19
1.E+20
1.E+21
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Depth (m)
L
o
g
(
C
o
n
c
e
n
t
r
a
t
i
o
n

(
c
m
-
3
)
)
n
p
Metrology for Developing Diffusion Models
Secondary Ion Mass Spectroscopy (SIMS)
1D chemical profiles
good sensitivity to all dopants
excellent depth resolution
surface region troublesome.
2D carrier profiling with excellent space resolution:
scanning capacitance microscopy (SCM)
+measurement affects sample
transmission electron holography (TEH)
+measures electrostatic potential
+difficult sample preparation.
Monte Carlo Diffusion Methods: Algorithm
Monte Carlo diffusion program (MARLOWE, UT-Austin) offers
accurate diffusion modeling.
MARLOWE
Generates initial I, V positions
THEORETICAL
CALCULATIONS
Energy of interactions
and
diffusion barriers
EXPERIMENTS
MONTE CARLO DIFFUSION CODE
- Diffusion
- Clustering
- I - V recombination
- Surface annihilation
- I, V trapping
- Boron kick-out, kick-in
Diffusion is critical to activate the implanted dopants
in the semiconductor devices.
Dopants diffuse in silicon by interacting with point
defects through a number of possible atomic-scale
mechanisms.
For short times, the diffusion is dominated by TED
because of high concentration of point defects.
Point defect concentrations depend on temperature,
Fermi level, implant damage, and surface processes
like oxidation.
1D/2D metrology is used to calibrate diffusion model.
Diffusion: Summary
Oxidation
Fundamentals of Thermal Oxidation.
Oxide Growth Model:
Deal-Grove Model
Thin Oxide Model.
Oxidation Chemistry.
Oxide Flow:
Oxidation-induced Stress
Visco-elastic Model.
Summary.
Oxidation: Diffusion, Reaction, Flow
Oxidation proceeds by three sequential processes:
oxidant diffuses through existing oxide
oxidant reacts at silicon surface to create new oxide
overlying oxide flows to accommodate new volume.
Process is at first limited by reaction but diffusion
through growing oxide becomes limiting.
O
2
or H
2
O ambient
Oxidant
Reaction
zone
Nitride
Silicon
Oxidation: Deal-Grove Model
C
0

C
L

Silicon SiO
2

( )
L
C C
D F
L
diff
0
=
F
reac
= kC
L

D = diffusivity of oxidant
C
L
= concentration at Si-SiO
2
interface
C
0
= concentration at the SiO
2
surface
L = oxide thickness
k = interface reaction rate constant
Oxidation: Deal-Grove Model
C
0

C
L

Silicon SiO
2

( )
L
C C
D F
L
diff
0
=
F
reac
= kC
L

At equilibrium: F
diff
= F
reac
, C
L
= C
0
/ [1 + kL/D]
Oxidation growth rate is given by:
where

C* = equil. oxidant conc.; N
s
= # oxidant/cm
3
in oxide
B
L
A B
t
L
2 1
1
+
=
c
c
s s
N C k A B N D C B
*
; * 2 = =
Thin Oxide Models
Deal-Grove model does not fit the early part of
oxidation curve.
The data in thin regime can be fitted with an addition
to Deal-Grove model given by:

where and
C
0
~ 3.6x10
8
m/hr, E
A
~ 2.35 eV, and ~ 7 nm in <111>
or <100> oriented silicon substrates.
This model can be found in TCAD tools like SUPREM4.
|
.
|
\
|
+
+
=
c
c
L
C
B
L
A B
t
L
exp
2 1
1
|
.
|
\
|
=
kT
E
C C
A
exp
0
Oxidation - Planar Growth
Two-step oxidation
shows a significant
difference in oxide
density.
Planar growth generates an intrinsic stress in oxide
during growth process:
modest stress (3x10
9
dynes/cm
2
)
density increases (< 3%)
refractive index increases (1%) relative to fully relaxed
oxides.
First oxidation
Second oxidation
1100 C 800 C
900 C 900 C
AL grown in the second step varies depending on the
thermal history of oxide (not just on L).
Oxidation - Planar Growth
Intrinsic stress is an atomistic process.
Relaxes gradually with annealing at a rate which
steadily decreases.
Recent measurements show that relaxation rate is
independent of stress level.
History effects are not accounted for in most process
simulators.
Measured linear/parabolic coefficients describe
oxidation in a state of intrinsic stress.
1D stress already accounted for in one-step
oxidation.
Oxidation Chemistry
Oxidation rate coefficients are sensitive to ambient
additives:
steam 20 - 50 times faster than O
2

3% Cl
2
increases growth rate by 20 - 30%
100 ppm NF
2
increases growth rate by 2 - 5
heavy substrate doping increases rate by 2 - 10
according to the relation

all easily accounted for by building table of B, B/A vs.
additive or dopant concentration.
NO, NO
2
are not supported in most process TCAD tools.
2
0
|
|
.
|
\
|
+ + + =
i i i
n
n
d
n
p
c
n
n
b a
k
k
Oxide Flow
Oxide growing on a curved
surface must flow.

Resulting deformations (and stresses) can be large!
LOCOS top surface must stretch by 15 - 20%.

Elastic limit of glass << 1%
Si
3
N
4

Silicon
Oxide
Silicon
Old Oxide
New Oxide
Oxide Flow
Large deformations on a curved surface during
oxidation mean viscous flow must occur.
Viscous flow model used to model stress during
oxide growth includes:
incompressible viscous flow
linear elasticity.
Visco-elastic flow model:
allows oxide to be slightly compressible
eliminates pressure equation
offers a significant numerical benefit.
Visco-elastic Model: Stress Simulation
Oxide stress
after local
oxidation.
Length of
stress vector
amount of
stress.
Compression
Tension
SiO
2

Si
3
N
4

Oxidation: Summary
Basic growth mechanism of thermal oxide:
oxidant transport through the SiO
2
layer to Si/SiO
2

interface
chemical reaction at the interface to produce the new
layer of oxide.
The growth is linear parabolic law.
The basic Deal-Grove model is extended to explain:
thin oxide growth
mixed ambient oxidation.
Important effects of thermal oxidation include OED,
ORD, and impurity redistribution and segregation.
Bulk-Process Simulation: Summary
Accurate process models and TCAD tools are
extremely critical for continuous scaling of ICs .
Workstation performance is continuously improving
for cost-effective computer experiments.
Existing models and TCAD tools treat different
aspects of process simulation quite well.
As new understanding develops, new models are
incorporated in TCAD tools to improve predictability.
Successful process TCAD will require a firm grasp of
the controlling process physics.
Samar Saha

Device Simulation
Mumbai, India
Outline
Introduction.
Carrier Transport Models.
Inversion Layer Mobility.
Quantum Mechanical Confinement.
Discrete Dopant Effects.
Numerical Methods.
Summary.
Introduction
p-substrate
p-well
n+ n+
S
T
I

Poly
S
T
I

hot carriers
Non-local transport
(velocity overshoot)
QM tunneling
Electrostatics:
- 2D/3D effects
- discrete charges
Atomic
scale
effects
QM confinement
Surface scattering
Quasi-ballistic transport
A device TCAD tool solves a set of equations to deal with
various physical phenomena in semiconductor devices:
Introduction
Objectives of this session is to:
focus on the underlying physics and models for practical
application of device TCAD such as
+identify device physics issues for simulation
+discuss and compare simulation approaches
+identify
limitations
uncertainties
challenges.
Carrier Transport Models
A device TCAD tool generates device characteristics
by solving:
Poissons [V.D = (r)] + carrier transport equations self-
consistently.
Carrier transport models include:
drift-diffusion (DD) - standard
Monte Carlo (MC)
molecular dynamics
hydrodynamic (HD)
Boltzmann equation
quantum balance equations.
The basic concept in transport theory is the carrier
distribution function = f(r,p
x
,t).
f(r,p
x
,t) = probability of a carrier at the position r with
momentum p
x
at any instant t.
f(r,p
x
,t) is a Maxwellian
distribution function with:
area = carrier density, n(r,t)
the spread depends on
carrier temperature
first moment is velocity
second moment is kinetic energy.
f(r,p
x
,t)
p
x

Equilibrium
At equilibrium, f(r,p
x
,t) is symmetric around p
x
= 0.
If an e-field is applied along the negative p
x
direction:
electron distribution is distorted and displaced from the
origin
causes electron scattering.
Device TCAD challenge is to solve f(r,p
x
,t).
f(r,p
x
,t)
p
x

Equilibrium
f(r,p
x
,t)
p
x

Non-equilibrium
c
x

To solve for f(r,p,t) - Boltzmann Transport Equation
(BTE):
six dimensions
+three in position space
+three in momentum space
solution techniques:
+MC simulation
+spherical harmonics
+scattering matrix
+and so on.
Solving f(r,p,t), we can find the quantities that device
engineers deal with directly such as:
carrier density, n(r,t)
current density, J
n
(r,t)
energy current, J
E
(r,t)
average kinetic energy, u
n
(r,t)
electron temperature, T
n
(r,t)
heat flux, Q
n
(r,t).
Six-dimensional equation is difficult to solve and
computationally demanding.
In TCAD, we directly solve for the quantities of interest.
Carrier Transport: Balance Equations
Basic idea to solve for a quantity (n
|
) of interest is to
formulate a balance equation such as:
rate of increase in n
|
= rate n
|
flows into the volume + net
generation rate.
| | |
|
R G F
t
n
+ - V =
c
c
Examples:
n
|
= n(x,t): continuity
equation.
n
|
= J
nx
(x,t): current
equation.
|
R
|
G
|
n
|
F - V
Assuming slowly varying time, we can write the
current equation:

where

t = average time between collisions
m* = effective mass of electrons.
We need a balance equation for kinetic energy, u
xx
.
For simplicity of computation:
approximate the effects of scattering in
n

close the balance equations by approximating u
xx
.
( )
x
q nu
qn J
xx
n x n nx
c
c
+ =
/ 2
c
* / )] , , ( [ m q t p r f
n
t =
Carrier Transport Models: Drift-Diffusion
The simplest solution of carrier transport equation is
local field or DD approach.
In DD, is determined by scattering, scattering is
determined by u
xx
, and u
xx
is determined by c.
For high fields in bulk silicon, c(x) and u
xx
are
constants or slowly varying:
here
n
=
0
[N,T
L
,c(x)]; D
n
= (k
B
T
L
/q)
n

Then the current equation is given by:

Local field transport model: [
n
= f(local field)]
( ) ( ) ( ) ( )
dx
dn
T k x t x qn t x J
n L B x n nx
c c c + = ) ( , ,
Carrier Transport Models: Drift-Diffusion
DD solution fails to predict device characteristics for
small geometry (s 0.1 m) MOSFETs.
We know:

here <t> is related to the average carrier energy,
u
n
(T
n
) and T
n
= local electron temperature.
Thus, the DD-transport model can be improved by
assuming,
n
as a function of local energy.
Local energy transport model:
n
= f(local energy)
Alternatively,
n
=
0
[N,T
L
,T
n
]
* / )] , , ( [ m q t p r f
n
t =
Carrier Transport Models: Local Energy
Solve for energy density, n
|
= W(x,t) = nu:

where t
E
= relaxation time.
n
|
= J
E
(x,t):

Unknowns: c(x), n(x), p(x), u
n
(x), and u
p
(x)
( )
(
+ =
dx
n D d
q x n T k C t x J
n
x n e B E Ex
) (
) ( , c
( )
E
x nx
Ex
u u n
x J
dx
t x dJ
t
c
) (
) (
,
0
=
increase in
energy flux
input e-field rate of energy
dissipation
Carrier Transport Models: DD vs. HD
DD vs. HD model data deviate significantly for 40 nm devices.
Macroscopic Transport Models: Summary
Models are derived directly from BTE.
Require numerous simplifying assumptions: closure,
scattering.
Difficult to assess the validity of assumptions.
Many flavors: HD, energy transport (ET).
Beyond DD, adds significant numerical complexity.
HD/ET generally provide good estimates of:
average carrier energy
current density.
Significant differences between various models.
Carrier Transport Models: MC Simulation
MC is a rigorous transport model.
The essence of the model is:
c q
dt
dp
=
electron
r
1

r
2

r
3
, r
4
r
1

r
2

r
3
, r
4
r
1

r
1
: free flight duration
r
2
: scattering event
r
3
: direction after scattering r
4

MC Simulation: Summary
Advantages:
numerical method for solving the BTE with e-e
correlation
advanced physics is readily treated (e.g. scattering and
complete band structures)
most reliable transport method for treating hot electron
distributions and for assessing novel devices.
Disadvantage:
computationally demanding:
+under near-equilibrium conditions
+for examining rare events.
Carrier Transport Models: Quantum
Different techniques available include:
(1) equilibrium or ballistic transport

+simplest form is used for MOS capacitor simulation
(2) wave propagation with phase randomizing scattering
+non equilibrium Greens function approach (Wigner
functions, density matrix)
(3) density gradient/QM potential approach
E r E
m
C
= + V ) (
* 2
2
|
|
.
|
\
|
V
V
|
|
.
|
\
|
+ V + V =
n
n
qm
n qD V nq J
n
n
n n n
2
*
2
6

Carrier Transport Models: Summary
Drift-diffusion (local field model):
= f(local field)
Balance equations (mostly local energy):
= f(local energy)
Examples: HD, ET, etc.
Boltzmann solvers:
MC
Quantum transport:
Schrodinger-Poisson
density gradient / quantum potential.
Inversion Layer Mobility
Choice of mobility model
can significantly alter the
simulation results.
Inversion layer mobility
versus effective normal
electric field show well-
known characteristics:
high fields: universal
behavior independent of
doping density.
low fields: dependent
on 1) doping density
and 2) interface charge.
Mobility versus effective normal electric field curve is
modeled using three components:
coulomb scattering (due to ionized impurity)
phonon scattering - almost constant
surface roughness scattering (at Si/SiO
2
interface).
At low normal fields:
less inversion charge density
ionized impurity scattering dominates and
eff
= f(N
A
).
At high normal fields:
higher inversion charge density close to the interface
surface roughness scattering dominates.
For higher normal fields, universal behavior as a
function of effective normal field:

The effective field is a non-local quantity.
Local field mobility models preferred for device
TCAD should produce universal behavior in terms of
the computed effective field.
Example:
+Lombardi Surface Mobility Model.
( )
depl S
Si
eff
N N
K
q
+ ~ 5 . 0 c
For ultra-thin gate oxide thickness the inversion layer
carrier wave function can extend through Si/SiO
2

interface to SiO
2
/polysilicon interface.

Mobility may depend on the surface roughness of
SiO
2
/polysilicon interface remote interface
roughness scattering.
p-substrate
p-well
n+ n+
S
T
I

NMOS
S
T
I

Poly
Gate Oxide
Electron
wave function
Choice of Surface Mobility Models
Inversion Layer Mobility: Summary
Mobility is extremely critical for advanced MOSFET
device simulation.
Choice of mobility model can effect simulation data.
Local field mobility models are being extended for
high normal fields and high doping densities.
New effects may begin to be felt in ultra-thin oxide
devices
Example:
+remote interface scattering.
Quantum Mechanical Confinement
The charges near the silicon surface are confined to
a potential well formed by:
oxide barrier
bend Si-conduction
band due to applied
gate potential.
Due to QM confinement of
charges near the surface:
energy levels are grouped in discrete energy sub-bands
each sub-band corresponds to a quantized level for
carrier motion in the normal direction.
E
C
(y)
Depth into Si (y)
E
F

E
n
e
r
g
y

Due to QM confinement, the inversion layer
concentration:
peaks below the SiO
2
/Si interface
~ 0 at the interface and is determined by the boundary
condition for the electron wave function.
Depth into Si (y)
n
(
y
)

Classical
Quantum
Az
Az = shift in the centroid of
charge in silicon away from
the interface.
Equivalent oxide thickness for
Az is:
z QM T
Si
OX
OX
A = A
c
c
) (
Classical:
C
Si
>> C
OX
(accumulation / inversion)
C
total
~ C
OX
Quantum:
C
Si
~ c
Si
/Az
C
total
< C
OX
Impact of QM confinement:
V
th
since more band bending is required to populate the
lowest sub-band
T
OX
eff
since a higher V
G
over-drive is required to produce a
given level of inversion charge density
C
total
+ since T
OX
eff
= T
OX
+ (c
OX
/c
Si
)Az.
C
ox
C
Si
V
gate
QM Confinement: Modeling Approach
van Dorts model: amount of band-gap widening due
to splitting of energy levels is given by:

where
B = constant
y = distance from Si/SiO
2
interface
y
ref
= reference distance for the material
E
n
= normal electrical field
and,
( )
ref n
semi
g
y y F E
kT
B y E /
4
) (
3
2
3
1
|
.
|
\
|
= A
c
) ( )) ( 1 (
2
y F e
n
y F
n
n
kT
E
CL
i
CL
i
i
g
A
+ =
QM Confinement: Modeling Approach
Modified local density approximation (MLDA):
robust and efficient formulation to compute quantization
of carrier concentration near Si/SiO
2
interface
offers a good compromise between the accuracy and
simulation time
the confined carrier density is given by FD statistics

| |
| |
( )
(
+ =
+
|
.
|
\
|
=
}
) (
) (
) ( ) ( ) (
and,
2 ( 1
exp 1
2
) (
1
2 1
0
0
y N
y n
kTF y E y E y E
y j
kT E
d N y n
c
QM
F c g
n
F
C QM
q
q
q
q
t
QM Confinement: C
OX
Reduction
Simulation data obtained by simulation program TSUPREM4
QM Confinement: T
OX
Measurement
4
5
6
7
8
2 3 4 5 6
T
OX
(nm)
A
T
O
X
/
T
O
X

(
%
)
AT
OX
T
OX
eff
- T
OX
QM Confinement: Effect on V
th

V
th
increase due to QM effect depends on channel doping, N
ch
.
Maximum increase in V
th
~ 100 mV for N
ch
~ 1x10
18
cm
-3
.
0.00
0.02
0.04
0.06
0.08
0.10
0 5 10 15 20 25 30
Transition Depth (nm)
V
t
h
(
Q
M
)

-

V
t
h
(
C
L
)

(
V
)
nMOSFETs
L
eff
= 100 nm; T
ox
= 3 nm
V
DS
= 50 mV; V
BS
= 0
1e18
uniform
1e17
GR
AR
ST
N
c
h

(
c
m
-
3
)

Transition
depth
1E18
1E17
GR-Graded
Retrograde
1E18
1E17
AR-Abrupt
Retrograde
1E18
1E17
Depth
Conventional
Step, ST
QM Confinement: Effect on I
ON

0
5
10
15
20
0 5 10 15 20 25 30
Transition Depth (nm)
A
I
o
n
(
C
L
-
Q
M
)
/
I
o
n
(
C
L
)

(
%
)
nMOSFETS
L
eff
= 100 nm; T
ox
= 3 nm
V
GS
= V
DS
= 1.5 V; V
BS
= 0
GR
AR
ST
1e18
uniform
1e17
I
on
decrease due to QM confinement depends on N
ch
.
Maximum drop in I
on
~ 20% for N
ch
~ 1x10
18
cm
-3
.
QM Confinement: Summary
Impact of QM confinement becomes significant for
T
OX
< 4 nm.
QM confinement affects:
T
OX
measurement
drive current
scaling limits.
Modeling approaches:
semi-physical (e.g. van Dort)
quantum potentials - MLDA
1D self-consistent Schrodinger-Poisson.
Discrete Dopant Effects
The volume of active
channel region for an
advanced MOSFET:
V = (W) x (L) x (X
j
)
Typically:
length, L = 40 nm
width, W = 100 nm;
junction depth, X
j
= 25 nm;
N
channel
= 1x10
18
cm
-3

N
tot
= 100 impurity atoms.
The number of dopants in V is a statistical quantity.
V
P (N
A
cm
-3
)
X
j

Discrete Dopant Effects
Effects of discrete dopants:
significant threshold (V
th
)
variation, o
V
th
(10s of mV)
lower average V
th
(10s of
mV)
asymmetry in drive current,
I
DS
.
3D transport leads to inhomogeneous conduction in
sub-100 nm devices.
Continuum diffusion models are inadequate to model
discrete dopant effects in sub-100 nm MOSFETs.
-
-
-
-
-
-
-
-
-
-
-
-
-
- -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- -
-
-
-
-
-
-
-
-
Discrete Dopant Effects: Summary
2D continuum models can predict spread in V
th
.
Full 3D simulation is necessary to predict mean.
The role of continuum versus granular models will
become increasingly important as devices continue
to shrink.
Hot Electron Effects
Effect:
hot electron injection.
Outcome:
substrate current.
Trends:
power supplies are decreasing
electric fields are increasing.
Hot-Carrier Effects
Channel electron
traveling through
high electric field
near the drain
end can:
become highly energetic, i.e. hot
cause impact ionization and generate e
and holes
+holes go into the substrate creating substrate current, I
sub
.
Some channel e
have enough energy to overcome the

SiO
2
-Si energy barrier generating gate current, I
g
.
The maximum e-field, E
m
near the drain has the greatest
control of hot carrier effects.
Gate
I
g

n+ Drain n+ Source
I
sub

m
hole
hot e

l
l l l l l l
Hot Electron Effects: Substrate Current
Local field model (DD)

c
c
= critical electrical field ~ 1.2 MV/cm
o = impact ionization coefficient.
calibration of impact ionization model parameters are
required to match silicon data
tuned parameter values can be non-physical and non-
predictive for a new technology.
( ) ( )
c
c
o c o
c o
c
n
e
q
J
r r G
n
=
|
.
|
\
|
=
) (
] [
Hot Electron Effects: I
sub
using DD Model
DD simulation results with default I
sub
model parameters do not
match the measurement data.
Hot Electron Effects: Substrate Current
Local energy model (HD / ET model)

surface impact ionization
better predictive capability than DD approach, but still
uses tuned parameters.
Non-local energy model.
Full band MC.
( ) ( )
) ( ) (
] [
bulk MOSFET
q
J
r u r G
n
n n
o o
o
<
|
.
|
\
|
=
Hot Electron Effects: Summary
Local field models are highly unphysical that result in
unphysical calibrated parameters.
Local energy models are more physical, but still
require calibration of model parameters.
Physically sound models that provide accurate
results without calibration of model parameters are:
full band MC
non-local energy transport models.
Device TCAD: Summary
As devices scale down to 0.1 m and below, new
physical effects are coming into play.
Existing tools treat different aspects of device
simulation fairly well.
No single tool treats all of the important physics.
Successful device TCAD will require a firm grasp of
the controlling device physics.
Samar Saha

Industry Application: Calibration of
Process and Device Models
Mumbai, India
Outline
Objectives.
Technology and Industry Trends affecting TCAD.
TCAD Challenges.
TCAD Tool Set.
Calibration:
Process Models
Device Models.
Mesh Generation.
TCAD in Technology Development.
Summary.
Objectives
Present issues and solutions for industrial TCAD:
process simulation
+calibration
device simulation
+key physical models
mesh generation
+optimal approach
calibration examples
+submicron process
+submicron device.
Industry Trends affecting TCAD
CMOS logic as technology driver:
CMOS logic technology design-space much larger than
that of DRAM or BJT technologies
CMOS logic generation life-span is extremely short
CMOS simulation is essentially 2D.
Logic technology offerings becoming broader:
high-V
th
devices
thick-oxide devices
low-V
th
devices.
System-on-a-chip (SOC) and logic derivatives:
integration issues driving increasing share of TCAD
cycles
+integrating memory and logic (NVRAM, DRAM)
+BiCMOS
+CMOS imaging
+SiGe BJT and PFET.
Net result:
Rapidly expanding opportunities for TCAD to contribute.
Rapid thermal processing (RTP):
easy process addition increases design space
many subtle electrical effects.
Larger wafer sizes:
interaction of process variations on circuit performance
becoming increasingly important new TCAD arena.
New impurity species increase design options:
In
Ge
N.
New materials and methods:
nitrided gate oxide
high-K gate dielectric
junction pre-amorphization
SOI
selective epitaxial growth
laser thermal annealing (LTA).
Net result:
rapidly expanding design space for TCAD to cover
process TCAD challenges predominate.
Industrial TCAD Challenges
Challenge is to transform TCAD potential into
valuable results for process and device engineers.
Key tasks:
system perspective
+connect process recipes to device parametric/circuit
performance (virtual fab)
+organize TCAD process to make non-experts productive
TCAD users and maximize productivity of experts
process and device simulations
+process simulation reflect actual process results
+accurate electrical results for compact model extraction.
Industrial TCAD Challenges
Critical assumptions for success:
calibrate/characterize complex physical models for the
present range of operation - global calibration
timely development/implementation of required physical
models
timely calibration (local calibration) of process and device
models to contribute significantly for the next generation
+technology development
+technology transfer.
TCAD usage can be significantly broadened.
TCAD Tool Set
Process simulation:
2D capability with
+extensive detailed physical model set for implantation,
diffusion, oxidation, deposition, and etching
+detailed knowledge of model formulation and
modification.
examples based on
+vendor supported SUPREM4-process platform
+generalized calibration procedure.
TCAD Tool Set
Device Simulation:
general 2D capability based on moments of Boltzmann
equation
control-volume discretization of DD/HD equations
examples based on
+vendor supported MEDICI-device platform
+generalized calibration procedure
user environment
+vendor supported TWB-framework platform.
Calibration - Role of TCAD
TCAD in research:
evaluate advanced device options
understand device physics.
TCAD in technology development (TD):
perform tradeoffs for design options to reduce
experimental wafer starts
assess manufacturability and design options
diagnose device/layout problems.
TCAD in manufacturing:
process simplification for production technologies
problem diagnosis and fix.
Accuracy is crucial, especially, for TD and manufacturing.
Need for Calibration
Deviation of simulation and measured data:
technology dependent:
+different focus area and application
+different physical models involved.
site/fab dependent:
+equipment
+material
+environment
+measurement techniques
+human interface.
Need for Calibration
Limitation of physical models:
secondary mechanisms become important
model dependency on implementation details
model short-fall in describing the target generation of
process technology and devices.
Limitation of model characterization/range:
may not cover all possible process conditions
may not cover all technologies
may not be able to measure directly.
Calibration Challenges
Experimental data:
expensive to obtain, especially, SIMS profiles
insufficient processing information
statistical fluctuations.
Model complexity:
some parameters can not be directly measured
more parameters than data points.
Simulation accuracy:
grid dependency
practical limitation on CPU and memory.
Objective of Tool Calibration
Device specific calibration:
operation region (optimization)
technology development
items of importance.
DOE and characterization.
Calibration of model parameters.
Supporting software utilities.
General Calibration Methodology
Use short flows to characterize process profiles:
design process splits to cover design space.
Use full flows to characterize devices with different
dimensions (L and W dependencies).
Tool calibration:
match SIMS profiles
use device data to correlate 2D effects
match device characteristics.
Two-phase process.
Process Simulation Overview
Model calibration for process simulation:
overview of calibration process
Phase 1: 1D impurity calibration
+methodology
+example - nMOSFET channel profile
Phase 2: 2D calibration (process + device)
+methodology
+example - reverse short channel effect (RSCE).
Summary.
Process Modeling Approach
Predictive capability for a wide range of logic and
memory technologies necessitates:
new implant tables with new species like In, Ge etc.
3-stream TED model for dopant, interstitials, and
vacancies
plus-n damage model with accumulated damage from
multiple implants
amorphization due to implant damage
transient activation/deactivation of dopants
dislocation loops as source/sink for interstitials
3-phase segregation model.
Process Simulation Calibration: Overview
Model calibration (Phase 1)
implant models
diffusion models
oxidation models
etch/deposition models.
TEM/SEM cross-sections, SIMS profiles, key (1D)
electrical parameters.
Technology/2D calibration (Phase 2)
key process model parameters
selected set of 2D electrical parameters.
MOSFETs Process Model Calibration Flow
Match SIMS profiles
Adjust for dose loss
Match V
th

RSCE
Two-dimensional Calibration
DIBL
Surface recombination
Damage by S/D implant
One-dimensional Calibration
Implant moments/table
OED
Segregation (set by channel profile)
Diffusivity (in oxide for dose loss)
T
ox
(QM,Poly-depletion corrections)
One-dimensional Calibration
Diffusivity of dopant-defect pair
Diffusivity of defects
MOSFETs 1D Process Model Calibration
p-substrate
p-well n-well
n+
PMOS
n+ p+ p+
STI
NMOS
A B C F E D
Cross-section for short loop experiments:
A / D NMOS / PMOS channel
B / E NMOS / PMOS SDE
C / F NMOS / PMOS S/D.
A Typical Short Loop Experiment for P-Well
Wafer No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Sacrificial oxide x x x x x x x x x x x x x x
P-Well (B) implant x x x x x x x x x x x x x x
N-PT (B) implant x x x x x x x x x x x x x
Well drive x x x x x x x x x x x x
nV
th
(BF2) implant x x x x x x x x x x x
Gate oxidation x x x x x x x x x x
Poly re-oxidation x x x x x x x x x
RTA1 x x x x x x x x
Spacer dep/etch x x x x x x x
S/D oxide x x x x x x
N+ (As) implant x x
RTA2 x x x
Calibration Example: Channel Profile
Use of detailed physical models to achieve 1D SIMS
profile fit:
typical Phase-1 calibration activity
model updated over several technology generations.
Channel profile after complete technology thermal
cycle.
Initial approach for implant and diffusion
MC implant
+significant CPU burden
scaled solid solubility
physics-based implant moments / implant table update.
Example: NMOS Channel Profile
P-Well B, 1E13 @ 200 KeV
after spacer deposition/etch
Depth (m)
l
o
g
1
0

(
B
o
r
o
n
)

SIMS
Simulation
Technology Calibration - Phase 2
Coupled process and device simulations using
Phase 1 calibration data.
Target output (electrical) parameters:
C - V curves
V
th

RSCE.
Input variables (5 - 8 process model parameters):
point-defect distributions from implants
+plus-n model
key impurity segregation coefficients
parabolic oxidation rate.
2D Calibration Example: RSCE
Process Modeling: Summary
Systematic process model calibration methodology
is critical.
Observed success within a (CMOS) technology:
process re-optimization offered a significant improvement
in device performance
process centering achieved at manufacturing co-location
with minimum development effort.
Observation:
each successive technology generation requires a
significant calibration effort (model update).
Device TCAD
Role of device simulation in TCAD
Key physical models and examples:
mobility models for deep sub-micron CMOS
quantum effects in scaled CMOS devices
DD model.
Device model calibration:
impact ionization with DD model.
Summary.
Device Simulation Role in TCAD
Simulate device electrical behavior with sufficient
accuracy to calibrate process simulation models:
primarily 2D electrostatic simulation
+V
th
, DIBL, I
off
, body effect, capacitances
expect DD model is sufficient for most requirements for
MOSFETs with L
eff
> 0.1 m.
Provide capability for the physical simulation of wide
range of device parameters:
substrate current, latch-up, ESD, and so on.
Support exploratory device simulation for research.
Device Simulation: CPU Burden
Numerical issues associated with device simulation
are well established:
core issue is repeated solution of large, sparse, ill-
conditioned, non-symmetric sets of linear equations
typical industrial CMOS problem:
+~ 10,000 mesh nodes
+simultaneous solution for (, n, p)
iterative solution methods often exhibit lack of
convergence on problems of industrial interest.
Optimized direct solution methods along with optimal
mesh generation techniques can reduce CPU
burden significantly without sacrificing accuracy.
Critical TCAD Models: Carrier Mobility
Device-design trends arising from CMOS scaling
require consideration of:
coulombic scattering in the inversion layer
+high substrate/channel doping levels
+channel doping can vary significantly across the device
inversion- and accumulation-layer mobility.
Industrial use of a mobility model requires:
strictly local calculation of mobility
+minor increase in program complexity
+no restrictions on device geometries or device designs.
Critical Device TCAD Models: QM Effects
CMOS scaling requires inclusion of inversion-layer
QM effects in device simulation for:
thinner gate oxides
higher substrate doping.
Inversion-layer QM correction model must be:
strictly local calculation of required physical quantities
+minor increase in program complexity
+no restrictions on device geometries or device designs
acceptable CPU burden
no significant degradation in robustness.
Models: van Dort / MLDA.
MOSFETs: Device Model Calibration Flow
Work function
QM model
Low field mobility
High field mobility
Band to band tunneling
Impact Ionization
I
DS
vs. V
GS
(V
th
)
@ V
BS
= 0,V
DS
= 50 mV
I
sub
vs. V
GS

@ V
BS
= 0,V
GS
= 0

I
DS
vs. V
GS
(I
DS
vs. V
DS
)
@ V
BS
= 0,V
DS
= V
DD
I
DS
vs. V
DS

@ V
BS
= 0,V
GS
= 0

Example: Impact Ionization Model
DD-simulation over estimates I
sub
by more than an order.
Impact Ionization model calibration:
used calibrated process model (technology calibration)
used calibrated device models (device calibration)
calibrate impact ionization coefficients.
The electron impact ionization rate:

where
A
i
and B
i
are empirical constants
E
eff
= effective electric field due to non-local effect.
|
|
.
|
\
|
=
eff
i
i i
E
B
A exp o
For DD, transform the model in terms of local electric
field, E. Assume, E
eff
o E,
E
eff
= k
*
E
q

where
k and q are constants depending on the spatial variation
of E near the drain-end of the channel.
Substituting for E
eff
and defining B
i
k
*
|
i
q
, the
modified impact ionization coefficient is:

Optimize |
i
and q to fit the measurement data.
q
|
o
|
.
|
\
|
=
E
A
i
i i
exp
Calibrate device TCAD models: comparison of I - V data.
Simulation with calibrated impact ionization coefficients.
Simulation with calibrated impact ionization coefficients.
Device TCAD: Summary
Vendor supported device TCAD tools work very well
with the present applications such as:
MOSFET I - V and C - V characteristics for technology
development
+logic
+DRAM.
Model selection and calibration show good results
for sub-0.25 m technology development.
Device TCAD effectiveness depends on:
mobility model suitable for the target technology
inversion-layer QM effects.
Mesh Generation for Simulation
Role and Requirements.
Methods:
structured
quadtree
unstructured
hybrid.
Example:
typical MOSFET mesh and gridding considerations.
Summary.

Mesh Generation: Role and Requirements
Requirement is to support complete automation of
process-to-device simulation transition:
highest barriers to expanded TCAD usage are
+mesh generation
+process simulation accuracy.
Consistent and specialized grid distribution is an
important key to simulation of high-performance
MOSET devices:
resolution of inversion layers and depletion regions
resolution of mobility-model physical effects.
Mesh Generation: Role and Requirements
Requirements:
must accept device structures from detailed process
simulation
no restrictions on device structures
mesh generation approach must minimize computational
burden without compromising solution robustness and
accuracy
+key:
anisotropic grid-point distributions (the capability of
supporting extreme differences in grid-point spacing in
x- and y-directions).
Mesh Generation Methods
Methods Advantages Disadvantages
Structured:
- algebraic
- elliptic
- Precise grid control
- Smooth grid transition
- Supports anisotropic grid
scales.
- Requires significant
structural preprocessing
- Difficult to automate
- Large grid sizes.
Unstructured - Very general
- Easy to automate.
- Do not support anisotropic
grids
- Large grid size for industrial
problems.
Quadtree/Octree:
- isotropic
recursive
subdivision
- Very general
- Easy to automate.
- Needs advanced features to
support anisotropic grids
- Large grid size for industrial
problems.
Hybrid:
- recursive
subdivision for
anisotropy
- unstructured
mesh algorithm
- Very general
- Easy to automate
- Precise and smooth grids
- Supports grid scales
- Minimizes mesh sizes
- Minimizes CPU burden.
- Need to identify different
regions for gridding prior to
device simulation.
Hybrid Mesh Generation: Half-MOSFET
x
y
Gate S/D
C
h
a
n
n
e
l

Source/Drain
Mesh Generation
Dependence of device performance on vertical grid-spacing.
Mesh Generation
Dependence of device performance on horizontal grid-spacing.
Mesh Generation: Summary
Mesh generation is the critical component of an
effective TCAD system.
Simulation results vary significantly on mesh and
may result in:
unphysical calibration parameters
unpredictable/inconsistent results.
Robust mesh:
allows process simulators to be consistently and robustly
linked to device simulators by non-experts
significantly reduces CPU burden for device simulation.
Industry Application: Summary
Vendor supported TCAD tools offer most simulation
capabilities for industrial usage.
Systematic calibration procedure is required to
support efficient:
process technology optimization
future technology development.
Mesh generation is crucial for predictive technology
simulation.
Well calibrated physical models provide efficient
predictive TCAD capability.
Samar Saha

Industry Application: TCAD in Device
Research and Compact Modeling
Mumbai, India
Research Application: Overview
Role of TCAD in device research:
how it differs from development/manufacturing.
examples
+sub-100 nm MOSFET device design
+design optimization of FinFETs.
TCAD for compact modeling:
TCAD-based compact model parameter extraction for
substrate current modeling
flash memory cell macro model.
Summary.
Role of TCAD in Research
Performance analysis of future device design
options to guide development effort.
Understand device physics for new device concepts.
Typically, research TCAD is not the virtual fab
paradigm:
process simulation is not used, since device cannot be
made with current process technologies.
Circuit performance is directly evaluated from the
output of device simulation using two different ways:
1 device simulation model extraction circuit simulation
2 mixed-mode device/circuit simulation.
Example: Sub-100 nm MOSFET Design
Design issues in achieving MOSFET devices near
the lower limit of channel length:
scaling requirements
material limitations of scaling
feasibility of continuous scaling.
Methodology to generate sub-100 nm MOSFET
device characteristics vs. scaling parameters.
Results and discussions.
Summary.
Scaling Requirements vs. Limitations
Scaling Requirements Present Limitations
A reduction in gate oxide
thickness, T
OX
in proportion to
the gate length, Lg to:
- control threshold voltage, V
th
- control drain-induced barrier
lowering (DIBL)
- improve drive current, I
DSAT
.
SiO
2
-T
ox
(eff) > 2 nm to maintain:
- tolerable chip standby power ~
100 mW range
- tolerable direct-tunneling gate
leakage current, Ig ~ 1 A/cm
2
- off-state leakage current, I
off
~ 1
nA/m.
A reduction in source-drain
extension junction depth, X
j
with scaling Lg to control:
- short channel effect (SCE).
X
j
> 30 nm to maintain:
- lower source-drain series
resistance, R
SD
- higher I
DSAT
.
A reduction in Lg to:
- improve device performance.
Lg > 60 nm to maintain:
- X
j
> 30 nm
Feasibility of Continuous T
OX
and X
j
Scaling
Scaling T
ox
(eff) < 2 nm is feasible with a highK
dielectric gate material to maintain:
a thicker value of T
OX
(physical) for a tolerable value of Lg
a target value of gate capacitance (C
OX
) equivalent to
that of an ultra-thin SiO
2
gate material.
Scaling X
j
< 30 nm is essential to:
scale down Lg, gate area, and C
OX

improve ac device performance.
Idealized Device Simulation Structure
Channel doping profile: vertically and laterally non-uniform.
SDE: heavily-doped source-drain extension regions with
junction depth X
j
.
DSD: heavily-doped deep source-drain of junction depth X
jd
.
Halo: channel-type doping around SDE regions.
L
eff

Halo
X
jd

X
j

Halo
DSD
SDE
L
ext
T
OX

Lg
Body (B)
Poly-Si gate
Spacer
Design Simulation Experiment
Designed CMOS technologies for L
eff
= 25 nm with:
{Lg = 40 nm, X
j
~ 14 nm, T
ox
(eff) = {1,1.5, 2} nm}
{Lg = 50 nm, X
j
~ 20 nm, T
ox
(eff) = {1,1.5, 2} nm}
{Lg = 60 nm, X
j
~ 26 nm, T
ox
(eff) = {1,1.5, 2} nm}.
For each technology:
non-uniform vertical channel doping profile was
optimized for the target long channel |V
th
| ~ 0.23 V
two halo profiles (double halo architecture) were used to
+reduce DIBL from both SDE and DSD regions
+achieve non-uniform lateral channel doping profile with
the target |I
off
| ~ 10 nA/m @ |V
DD
| = 1 V.
Simulation Strategy
Optimized technology parameters:
SDE peak concentration ~ 2.5x10
20
cm
-3

DSD peak concentration ~ 3.7x10
20
cm
-3

peak halo concentration ~ 5x10
18
-

1x10
19
cm
-3
.
Channel concentration dependent on Lg.
Device characteristics were generated using MEDICI
with:
hydrodynamic model for semiconductors
van Dorts Quantum Mechanical model
calibrated device models (global calibration!!).
Simulated Channel Doping Contours
Lg
-0.45
-0.35
-0.25
-0.15
-0.05
0.05
0.15
0.25
0.35
0.45
10 20 30 40 50 60 70 80 90 100
L
eff
(nm)
V
t
h

(
V
)
Tox(eff) = 2.0 nm
Tox(eff) = 1.5 nm
Tox(eff) = 1.0 nm
40 nm Technology; X
j
~ 14 nm
|V
DS
| = 0.05 V; V
BS
= 0
nMOSFET
pMOSFET
(a)
-0.45
-0.35
-0.25
-0.15
-0.05
0.05
0.15
0.25
0.35
0.45
10 20 30 40 50 60 70 80 90 100
L
eff
(nm)
V
t
h

(
V
)
Tox(eff) = 2.0 nm
Tox(eff) = 1.5 nm
Tox(eff) = 1.0 nm
60 nm Technology; X
j
~ 26 nm
|V
DS
| = 0.05 V; V
BS
= 0
pMOSFET
nMOSFET
(b)
|V
th
| increases with the increase in T
OX
(eff) for all devices.
Devices with L
eff
= 25 nm and T
OX
(eff) = 2 nm, |V
th
| > 0.4 V is
too high for high-performance operation @ |V
DD
| s 1 V.
T
OX
(eff) < 2 nm offers lower |V
th
| for low power operation.
Simulated V
th
vs. L
eff
for different

T
OX
(eff)
Simulated I
DSAT
vs. I
off
for different

T
OX
(eff)
Devices with |I
off
| ~ 10 nA/m represents L
eff
= 25 nm.
At a constant |I
off
| > 2 nA/m:
|I
DSAT
| increases as T
OX
(eff) decreases
T
OX
(eff) < 2 nm is essential to improve I
DSAT
for L
eff
= 25 nm
devices.
For a typical 50 nm technology with L
eff
= 25 nm and T
ox
(eff) = 1
nm:
S ~ 80 mV/decade
|DIBL| ~ 60 mV
I
DSAT
(n) ~ 680 A/m, |I
DSAT
(p)| ~ 275 A/m @ |V
GS
| = 1 V = |V
DS
|.
Simulated I - V Data for T
OX
(eff) = 1 nm
For 25 nm devices of a 50 nm CMOS technology, as T
ox
(eff)
increases from 1 nm 1.5 nm:
S increases [AS ~ 8 mV/decade]
DIBL increases [A(DIBL) ~ 30 mV]
|I
DSAT
| decreases [AI
DSAT
(n) ~ 102 A/m; AI
DSAT
(p) ~ 42 A/m].
OX
(eff) = 1.5 nm
For 25 nm devices of a 50 nm CMOS technology, as T
ox
(eff)
increases from 1 nm 2 nm:
S increases [AS ~ 16 mV/decade]
DIBL increases [A(DIBL) ~ 60 mV]
|I
DSAT
| decreases [AI
DSAT
(n) ~ 214 A/m; AI
DSAT
(p) ~ 72 A/m].
OX
(eff) = 2 nm
Simulated V
th
vs. X
j
for Different

T
OX
(eff)
-0.45
-0.35
-0.25
-0.15
-0.05
0.05
0.15
0.25
0.35
0.45
12 14 16 18 20 22 24 26 28
X
j
(nm)
V
t
h

(
V
)
Tox(eff) = 2.0 nm
Tox(eff) = 1.5 nm
Tox(eff) = 1.0 nm
|V
DS
| = 0.05 V; V
BS
= 0
L
eff
= 25 nm; |I
off
| ~ 10 nA/m
p
M
O
S
F
E
T
n
M
O
S
F
E
T
Simulated I
DSAT
vs. X
j
for Different

T
OX
(eff)
Simulated DIBL vs. X
j
for Different

T
OX
(eff)
10
30
50
70
90
110
130
150
12 14 16 18 20 22 24 26 28
X
j
(nm)
d
V
t
h
(
D
I
B
L
)

(
m
V
/
V
)
Tox(eff) = 2.0 nm (nMOSFET)
Tox(eff) = 2.0 nm (pMOSFET)
L
eff
= 25 nm
V
BS
= 0
Simulated S vs. X
j
for Different

T
OX
(eff)
60
65
70
75
80
85
90
95
100
12 14 16 18 20 22 24 26 28
X
j
(nm)
S

(
m
V
/
d
e
c
a
d
e
)
L
eff
= 25 nm
V
BS
= 0
Simulated Delay for Different X
j
and Lg
Sub-100 nm MOSFET Design: Summary
The simulation results show the feasibility of 25 nm
MOSFETs with:
T
OX
(eff) < 2 nm to
+maintain lower |V
th
| for |V
DD
| s 1 V operation

+achieve higher |I
DSAT
| for a target value of |I
off
|
+lower value of DIBL
+lower value of S ~ 80 mV/decade
X
j
< 30 nm to
+scale Lg < 60 nm
+improve device speed.
25 nm devices with X
j
~ 14 nm and Lg ~ 40 nm show
a significant improvement in speed.
Design FinFET (double-gate MOSFET) Simulation
Structure.
Optimize Different Fin-dimensions.
Feasibility of 20 nm FinFET Device.
Comparison of 20 nm Device Performance using
FinFET vs. Conventional MOSFET Architecture.
Summary.
Example: Double Gate MOSFET Design
Idealized Double Gate MOSFET Structure
T
ox

T
ox

T
Si
Source Drain
Top Gate
Bottom Gate
L
g

T
ox
= Top/bottom gate oxide thickness.
T
Si
= Un-doped/lightly-doped channel width.
L
g
= Channel length.
Simulated DG-MOSFET FinFET Structure
T
fin

Major Process Steps to Generate FinFETs
1
.

D
e
f
i
n
e

S
i
-
F
i
n

2
.

G
a
t
e

o
x
i
d
a
t
i
o
n

3
.

P
o
l
y
-
S
i

g
a
t
e

4
.

N
i
t
r
i
d
e

s
p
a
c
e
r

S
/
D

i
m
p
l
a
n
t

5
.

H
a
l
f
-
s
t
r
u
c
t
u
r
e

6. Full-structure
BOX
Nitride
Poly
Critical Parameters for FinFET Simulation
Parameters used for simulation structure design:
T
fin
= 10 to 30 nm
H
fin
= 50 nm
L
g
= 10 to 50 nm
T
ox
= 1.5 nm.
For device simulation, channel doping was optimized
to obtain V
th
~ 0.1 V for L
g
= 20 nm nFinFETs.
Device structures and the characteristics were
generated using 3D-simulation tool Taurus (from
Synopsys).
V
th
vs. L
g
for Different T
fin
; H
fin
= 50 nm
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
10 20 30 40 50
L (Gate) (nm)
V
t
h

(
V
)
Tfin = 10 nm
Tfin = 20 nm
Tfin = 30 nm
I
DSAT
vs. L
g
for Different T
fin
; H
fin
= 50 nm
S vs. L
g
for Different T
fin
; H
fin
= 50 nm
50
70
90
110
130
150
10 20 30 40 50
L (Gate) (nm)
S

(
m
V
/
d
e
c
a
d
e
)
Tfin = 10 nm
Tfin = 20 nm
Tfin = 30 nm
I V

Characteristics of

20 nm FinFETs

FinFETs vs. Conventional MOSFETs

Device
Parameters
Units FinFETs
Double-halo
MOSFETs
L
eff
nm 20 20
T
ox
nm 1.5 1.5
V
th
V 0.13 0.35
I
DSAT
(V
GS
= V
DS
= 1 V)
A/m
775 587
I
off
(V
GS
= 0, V
DS
= 1 V)
A/m
3 0.05
DIBL V 32 130
S-factor mV/decade 83 100
20 nm FinFETs show superior device performance
compared to 20 nm conventional MOSFETs.
TCAD is used to design and study FinFET device
characteristics.
The simulation data for nFinFETs with 10 nm < L
g
<
50 nm and H
fin
= 50 nm show:
higher V
th
roll-off as L
g
decreases for thicker T
fin
devices
lower I
DSAT
in thinner T
fin
devices due to higher s/d
resistance
increase in S with decrease in L
g
for T
fin
< 50-nm
S 60 mV/decade for all T
fin
with L
g
>>40-nm.
20 nm FinFETs show superior device performance
than 20 nm conventional bulk-MOSFETs.
FinFET Design: Summary
Example: Compact Model Extraction for I
sub

Procedure for TCAD-based Compact Model
Parameter Extraction.
Simplification of I
sub
Model for TCAD-based Compact
Modeling.
Model Extraction.
Model Verification.
Summary.
Substrate Current, I
sub
Model
I
sub
generated due to impact ionization is given by:

where
A
i
and B
i
are impact ionization parameters
l
c
= characteristic length of saturation region
E
m
= maximum lateral electric field near the drain

E
c
= critical electric field for velocity saturation.
, exp
(
=
m
i
DS m c
i
i
sub
E
B
I E l
B
A
I
2
2
c
c
DSAT DS
E
l
V V
+
|
|
.
|
\
|
=
sub
Model
At strong inversion (V
DS
>> V
DSAT
) E
m
is given by:

where

L
eff
= effective channel length of device
V
th
= threshold voltage of device.
( )
( )
th GS eff c
th GS eff c
DSAT
V V L E
V V L E
V
+
=
c
DSAT DS
m
l
V V
E
~
( )
(
=
DSAT DS
c i
DS DSAT DS
i
i
sub
V V
l B
I V V
B
A
I exp
sub
Model
The bias dependence of E
c
is given by:
E
c
= E
c0
+ E
cg
V
GS
+ E
cb
V
BS

where E
c0
, E
cg
, and E
cb
are model parameters given
by:
E
c0
= E
c
@ V
GS
= V
BS
= 0
E
cg
= slope of E
c
vs. V
GS
plot @ V
BS
= constant
E
cb
= slope of E
c
vs. V
BS
plot @ V
GS
= constant
The bias dependence of l
c
is given by:
l
c
= (l
c0
+ l
c1
V
DS
)\T
OX

here l
c0
and l
c1
are model parameters.
I
sub
Model Parameters
Empirical constants:
A
i
= 1.65x10
6
(1/cm)
B
i
= 1.66x10
6
(V/cm)
Technology dependent parameters:
E
c0
= bias independent constant (V/cm)
E
cg
= gate bias dependent parameter (1/cm)
E
cb
= back-gate bias dependent parameter (1/cm)
l
c0
= bias independent constant (\cm)
l
c1
= bias dependent constant (\cm/V).
We assume, l
c
= l
c0
is a technology dependent constant
for TCAD-based parameter extraction (i.e. ignore l
c1
).
TCAD-based I
sub
Model Extraction
V
DSAT
extraction
E
c
extraction
l
c
extraction
SPICE simulation
Format I - V data
Compute I
sub
/I
DS

Device
Simulation
Device Model
Calibration
At each V
GS
, generate:
I
DS
- V
DS
and I
sub
- V
DS

Process
Simulation
Process Model
Calibration
Generate:
Device Structure
Extraction of
{E
c0
, E
cg
, E
cb
}
Parameter Extraction: V
DSAT

V
DSAT
is extracted by mapping constant I
sub
/I
DS
contours on
I
DS
vs. V
DS
family of simulated curves.

Parameter Extraction: E
c0
, E
cg
, and E
cb

E
c0
and E
cg
extraction:
extract V
DSAT
for different values of V
GS
at V
BS
= 0.
compute E
c
from:

plot E
c
vs. V
GS
to extract:
E
c0
= intercept @ V
GS
= 0
E
cg
= slope.
Same procedure to extract E
cb
with V
BS
= 0.
( )
( )
th GS eff c
th GS eff c
DSAT
V V L E
V V L E
V
+
=
Parameter Extraction: l
c
and Components
The simplified from of the expression:
log(Y) = mX + C,
where
X = 1/(V
DS
- V
DSAT
)
Y = I
sub
/[I
DS
(V
DS
- V
DSAT
)]
Parameters are extracted from log(Y) vs. X plots:
slope, m = - B
i
l
c

intercept, C = ln(A
i
/B
i
).
( )
(
=
DSAT DS
c i
DS DSAT DS
i
i
sub
V V
l B
I V V
B
A
I exp
Parameter Extraction: l
c
and Components
TCAD-based I
sub
Models
For nMOSFET devices of the target technology:
+ E
c0
= 5.50E+04 (V/cm)
+ E
cg
= 3.50E+03 (1/cm)
+ l
c
= 1.38E-05 (cm)
+ A
i
= 1.65E+06 (1/cm)
+ B
i
= 1.66E+06 (V/cm)
Model Verification
Measurement and simulation data using the extracted models.
Model Verification
Measurement and simulation data using the extracted models.
Model Extraction for I
sub
: Summary
The example shows the basic idea to use TCAD for
compact model parameter extraction using:
calibrated process models for process TCAD
calibrated device models for device TCAD
simplified equations and extraction routines, as needed.
Process and device models were calibrated for the
target technology.
I
sub
model is simplified to extract model parameters.
The simulation data using TCAD-based model agree
very well with the measurement data.
Example: Flash Memory Cell - Macro Model

Flash Memory Cell Compact Modeling
split gate cell
two-transistor macro model
necessity for TCAD-based macro model.
Model extraction.
procedure.
Flash Memory Cell - Split Gate Structure
Cell consists of:
WL transistor
FG transistor.
FG may not have
contact pad for
measurement.
Typically, 1T-cell
model is used.
2T-model provides
more accurate cell
characteristics.
TCAD-based.
Flash Memory Cell: TCAD-based Model
Calibrated
Device Model
Calibrated
Process Model
Extract SPICE
Model for T1
Extract SPICE
Model for T2
Model Verification
Simulate
I - V for T1
Simulate
Test Structures
SPICE/Circuit
Simulation
Generate
Macro Model
C
a
l
i
b
r
a
t
e
d

D
e
v
i
c
e

M
o
d
e
l

Simulate
I - V for T2
TCAD in Research & Modeling: Summary
Device TCAD can be successfully used in device
research to:
study different device options
examine new device ideas
optimize device design range for technology
development guideline.
Calibrated TCAD models can be used accurately to:
predict device performance
extract compact model
predict circuit performance.
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MOSFETs: can we understand it?, App. Surf. Sci., vol. 39, p. 578, 1989.
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