VLSI System Design Methodology

Contents
Structure Design Strategy System on chip design

Sea of gate & Gate array design

Standard cell design Full-custom mask design

Structure Design Strategy

System on chip design

System on Chip Design options:

Programmable logic and structures, Programmable interconnect, Programmable gate arrays Sea of gate and gate array design

Standard cell design

Programmable Logic
In CMOS, the spectrum of programmable devices into 3 areas:
Chips with programmable logic structures Chips with programmable interconnect Chips with reprogrammable gate arrays

 The cmos system designer should be familiar with these options for two reasons:
First, it allows the designer to competently assess a particular system requirement for an IC and recommend a solution, given the system complexity, the speed of operation, cost goals, time-to-market goals, and any other top-level concerns. Second, it familiarizes the IC system designer with methods of making any chip design reprogrammable and hence more useful and of wider-spread use.

Programmable Logic Structures

 The programming of PALs is done in three main ways:

Fusible links UV-erasable EPROM EEPROM

Fusible links
Fusible links use metals such as
Platinum silicide Titanium tungsten to form the links These links are blown when current exceeds in the fuse. This is accomplished by using higher voltage than normal. Programming is a one time.

UV-erasable EPROM
UV-erasable memories typically use a Floating Gate. The floating gate is interposed between the regular MOS transistor and the channel.

To program the cell, voltage around 13-14volts is applied to the control gate. While drain of the transistor to be programmed is held at around 12volts.
Programming may be completed numerous times. The chips are usually housed in glass-lidded packages to allow illumination by UV light.

EEPROM
EEPROM technology allows the electrical programming and erasure of CMOS ROM cells. Two transistors are typically used in a ROM cell.
Access transistor Programmed transistor

 A two-poly sandwich is again used in the programmed transistor with the control gate on the top.

Series access transistor allows programming of cells. EEPROM has a testability advantage over fused technologies.

Programmable interconnect.
In PAL, the device is programmed by changing the characteristics of switching element. An alternative would be to program the routing. Commercially, programmable routing approaches are represented by products from
Actel QuickLogic

Antifuse
Based on an element called a PLICE or antifuse. Normally high resistance (> 100 M)
on application of appropriate voltage, the antifuse is changed permanently to a low resistance structure (200-500)

Antifuse-based Actel FPGAs

I/O Buffers Program/T est/Diagnostics V ertical routes

Standard-cell like floorplan

I/O Buffers I/O Buffers
I/O Buffers

Rows of logic modules Routing channels

Actel Interconnect
Logic Module

Horizontal Track

Anti-fuse

Vertical Track

Interconnection Fabric

 Pass transistors are used to connect wire segments for the purpose of programming. These may be bypassed by antifuses if the links are required permanently. N1,N2,N3,N4,N9,N10,N11 are column access transistors. N5,N6,N7,N8 are row access transistors. To program antifuse all transistors in series are turned on at end is connected to programming voltage and ground supply. When the programming sequence is applied, the antifuse so selected is blown.

Basic Block in Actel FPGA

 It consists 3 2-input muxes, nor gate. Implements 2 and 3 input logic functions and also 4 input functions. A latch also implemented using one logic element.

General Architecture of Xilinx FPGAs

RAM-based FPGAs
CLB CLB switching matrix Horizontal routing channel Interconnect point CLB CLB

Vertical routing channel

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Basic Block (CLB) in RAM-based FPGAs

Combinational logic Storage elements

R A B/Q1/Q2 C/Q1/Q2 D A B/Q1/Q2 C/Q1/Q2 D E Clock

Any function of up to 4 variables

Din
F

R D Q1 CE F G

Any function of up to 4 variables

R F G CE G D Q2

CE

Courtesy of Xilinx
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

RAM-based FPGA

Xilinx XC4025
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]

Programmable Logic: FPGA

Xilinx 4000 Interconnect

Switch Matrix

Sea of Gates
Uninterrupted lines of Pand N diffusions Metal interconnects over non used transistors Lines are interrupted connecting PMOS to Vdd and NMOS to Vss 2-5 masks till three levels of metals, vias, interconnects

Gate Array - Sea-of-gates

polysilicon VD D

rows of uncommitted cells

metal GND possible contact

Uncommited Cell

In 1 In 2

In 3 In4

routing channel

Committed Cell (4-input NOR)

Out

Sea-of-gate Primitive Cells

Oxide-isolation PMOS PMOS

NMOS

NMOS NMOS

Using oxide-isolation

Using gate-isolation

Standard Cell Design

SSI(nand,nor,xor,aoi,oai,inverters,buffers,regs) MSI(decoders,encoders,adders,comparators) Datapath(alus,adders,shifters) Memories(RAM,ROM,CAM) System-level bloks (processors, serial interfaces, etc.)

Standard Cell Libraries

Typically contain a few hundred cells inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches, and flip-flops Each gate type can have multiple implementations to provide adequate driving capability for different fanouts e.g the inverter gate can have standard size transistors, double size transistors, and quadruple size transistors the chip designer can choose the proper size to achieve high circuit speed and layout density Cells characterized for various metrics, such as delay time vs. load capacitance Circuit, timing, and fault simulation models cell data for place-and-route mask data Cells designed such that they can be abutted to form rows

Standard Cell Based Design

Feedthrough Cell Logic Cell

Rows of Cells

Routing Channel
Routing channel requirements are reduced by presence of more interconnect layers

Functional Module (RAM, multiplier, )

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]