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Introduction to the ARM Instruction Set

Instruction processes data held in registers and accesses memory with load and store instruction

data processing instructions, branch instructions, load-store instructions, software interrupt instruction, and program status register instructions.

Data Processing Instructions

manipulate data within registers move , arithmetic , logical , comparison, and multiply instructions. Suffix S on Data processing instructions updates flags in CPSR

Barrel
shift

Shifter

the 32-bit binary pattern in one of the source registers left or right by a specific number of positions before it enters the ALU, to increases the power and flexibility instruction for loading constants into a register and achieving fast multiplies or division by a power of 2.

useful

Move Instructions

Syntax: <instruction>{<Cond>}{S} Rd, N

N

is a register or immediate value destination register

Rd

MOV -Move a 32-bit value into a register -Rd = N

E.g.

mov r7,r5

MVN - move the NOT of the 32-bit value into a register- Rd =N

Data Processing Instruction With Barrel Shifter

e.g. mov r7,r5,LSL #2

Arithmetic Instructions

Syntax: <instruction>{<Cond>}{S} Rd, Rn, N

PRE

r0 = 0x00000000 RSB r0, r1, #0 ;

r1 = 0x00000077 Rd = 0x0 - r1

POST

r0 = 0xffffff89

Logical Instructions

Syntax: <instruction>{<Cond>}{S} Rd,Rn, N

logical instructions update the cpsr flags only if the S suffix is present

Comparison Instructions

Syntax: <instruction>{<cond>} Rn, N

Multiply Instructions

Syntax:
MLA{<cond>}{S} MUL{<cond>}{S}

Rd, Rm, Rs, Rn Rd, Rm, Rs

Syntax:
<instruction>{<cond>}{S}

RdLo, RdHi, Rm, Rs

long multiplies accumulate onto a pair of registers representing a 64-bit value

RdLo holds the lower 32 bits of the 64-bit result, and RdHi holds the higher 32 bits of the 64-bit result

Branch Instructions

Syntax:
B{<cond>}

label label Rm label | Rm

BL{<cond>} BX{<cond>}

BLX{<cond>}

Load-Store Instructions

transfer data between memory and processor registers three types of load-store instructions: singleregister transfer, multiple-register transfer,and swap.

Single-Register Transfer

Syntax:
<LDR|STR>{<cond>}{B} LDR{<cond>}SB|H|SH STR{<cond>}H

Rd,addressing1

Rd, addressing2

Rd, addressing2

Hw tht worksss.

LDR r0, [r1]

load

register r0 with the contents of the memory address pointed to by register r1.

STR r0, [r1]

store

the contents of register r0 to the memory address pointed to by register r1.

Single-Register Load-Store Addressing Modes

r0 = 0x00000000 r1 = 0x00090000 mem32[0x00009000] = 0x01010101 mem32[0x00009004] = 0x02020202

Preindex with writeback

calculates

an address from a base register plus address offset and then updates that address base register with the new address
r0 = 0x02020202 r1 = 0x00009004

preindex offset
same

as preindex with writeback does not update the address base register.

r0 = 0x02020202 r1 = 0x00009000

Postindex
used.

only updates the address base register after the address is

r0 = 0x01010101 r1 = 0x00009004

Multiple-Register Transfer

Syntax:
<LDM|STM>{<cond>}<addressing

mode>

Rn{!},<registers>{}

Load-store multiple instructions can increase interrupt latency Interrupt has no effect until the load-store multiple instruction is complete

Addressing mode for load-store multiple instructions.

Swap Instruction

Syntax: SWP{B}{<cond>} Rd,Rm,[Rn]

useful when implementing semaphores and mutual exclusion in an operating system

Software Interrupt Instruction

Syntax: SWI{<cond>} SWI_number

Sets program counter pc to offset 0x8 in vector table. forces the processor mode to SVC, which allows an operating system routine to be called in a privileged mode.

Program Status Register Instructions

Transfers contents of either the cpsr or spsr into a register,or in reverse direction. Together these instructions are used to read and write the cpsr and spsr Fields- can be any combination of control (c), extension (x), status (s), and flags (f ) relate to particular byte regions in a psr

Coprocessor Instructions

Syntax:

CDP{<cond>} cp, opcode1, Cd, Cn {, opcode2} <MRC|MCR>{<cond>} cp, opcode1, Rd, Cn, Cm {, opcode2} <LDC|STC>{<cond>} cp, Cd, addressing

cp field represents coprocessor number between p0 and p15. opcode -operation to take place on coprocessor. Cn, Cm, and Cd fields describe registers within coprocessor

ARMv5E Extensions

Conditional Execution

Thumb has higher performance than ARM on a processor with a 16-bit data bus, but lower performance than ARM on a 32-bit data bus, use Thumb for memory-constrained systems. On average, a Thumb implementation of the same code takes up around 30% less memory than the equivalent ARM implementation.

To call a Thumb routine from an ARM routine, the core has to change state. This state change is shown in the T bit of the cpsr. The BX and BLX branch instructions cause a switch between ARM and Thumb state while branching to a routine. The BLX instruction was introduced in ARMv5T. On ARMv4T cores the linker uses a veneer to switch state on a subroutine call

The conditional branch instruction is the only conditionally executed instruction in Thumb state.

Data Processing Instructions

Move instructions, arithmetic instructions, shifts, logical instructions, comparison instructions,and multiply instructions Most Thumb data processing instructions operate on low registers and update the cpsr ASR, LSL, LSR, and ROR are separate instructions

Thumb software interrupt (SWI) instruction causes a software interrupt exception. If any interrupt or exception flag is raised in Thumb state,the processor automatically reverts back to ARM state to handle the exception. SWI number is limited to the range 0 to 255 and it is not conditionally executed