Professional Documents
Culture Documents
TESTING DIRECTORATE
RESEARCH DESIGNS & STANDARDS ORGANISATION LUCKNOW
INTRODUCTION
Railway
structures
engineering
are
components/
to cyclic
subjected
important criteria in design. In fatigue testing lab we simulate the service loading condition to enable fatigue life prediction & design validation of rolling stock components & complex
structures.
OVERVIEW
Adequacy of new designs of Bogie frames for rolling stock
INFRASTRUCTURE
Working Principle
Control Data Acquisition
: Closed Loop Electro-Hydraulic Servo Controlled System : Computerised Control with Software
: 32 Channels 2 nos.
TYPES OF TESTS Life Cycle Test Stress investigation Load Deflection Characteristics Test
Assemblies and components tested Bogie Frames of locomotive, coaches and wagons Metal bonded rubber components like EM pads & Side bearer pads and brake beams for wagons Side bearer pads, coil springs, guide link, equalising Beam etc for locomotives Shock absorbers and rubber buffer springs for coaches Rail bridge sleepers for track
Atmega16 Microcontroller
Features
Advanced RISC Architecture Up to 16 MIPS Throughput at 16 MHz 16K Bytes of In-System SelfProgrammable Flash 512 Bytes EEPROM 1K Byte Internal SRAM 32 Programmable I/O Lines In-System Programming by On-chip Boot Program 8-channel, 10-bit ADC Two 8-bit Timer/Counters with Separate Presale's and Compare Modes One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Features
.Four PWM Channels .Programmable Serial USART .Master/Slave SPI Serial Interface .Byte-oriented Two-wire Serial Interface .Programmable Watchdog Timer with Separate On-chip Oscillator .External and Internal Interrupt Sources .Operating Voltages 4.5V - 5.5V for ATmega16 .Speed Grades 0 - 16 MHz for ATmega16 .Power Consumption @ 1 MHz, 3V, and 25C for ATmega16 Active: 1.1 mA Idle Mode: 0.35 mA Power-down Mode: < 1 A
Pin Configuration
Block Daigram
PROGRAM USED
// Program to indicate low water level #include<avr/io.h> #include<util/delay.h> int main(void) { DDRD=0x00; // initialize Port D as Input DDRA=0x01; // initialize Port A as Output while(1) { if((PIND & (1<<PD0))) { PORTA=0x00; // If Pin 0 Of Port D is High, Port A will be Low _delay_ms(2); // Delay of 2 ms } else if ((PIND | (1<<PD0))) { PORTA=~PORTA; // If Pin 0 of Port D is Low, Port A will attain value 01(Hex) i.e. High only at Pin 0 of Port A _delay_ms(2); // Delay of 2 ms } } }
Diagram