Comparison of the Behavior of MOSFET Transistors Described in Hardware Description Languages

Aravind Gurumurthy M.S Thesis Defense Presentation Committee Chair: Dr. Carla Purdy

Goals

Choose the correct transistor model appropriate

for a given application

Compare simulation results of Verilog-AMS

models with results from SPICE

Improve simulation time and accuracy

Thesis outline

MOSFET transistor MOSFET modeling Different generations of MOS models Experimental setup and models used Results Conclusions and future work

MOSFET transistor

MOSFET is a majority carrier device Can be of two types NMOS or PMOS

Fig 1 Top view of NMOS transistor, W= Channel width, L= Channel length

In NMOS transistor as shown, current carried from source to drain by electrons through the n-type channel

MOSFET parameters

The table 1 shows the most frequently used MOS parameters

Table 1 MOS parameters

Modes of operation

Cutoff region : VGS < VT

Resistive region:

VGS VT > VDS

ID = (kn. W)/(L)*[(VGS - VT)2 VDS2/2]

Saturation region:

VT < VGS and VGS VT < VDS

ID = (kn. W)/(L)*[(VGS - VT)2/2]

MOSFET history

MOSFET modeling dates back 35 years Initially based in V-I and V-C characteristics Modeling has become more complex Current models include effects from short channel and long field strengths

Steady increase in the number of model parameters over

almost four decades

MOSFET history

Source : http://legwww.epfl.ch/ekv/mos-ak/stuttgart/Pregaldiny-mos-ak-STR04.pdf

Fig 1 Number of model parameters Vs time

MOS modeling

Modeling can be defined as The method of finding the parameter values for fixed simulator model equations

MOS modeling -Writing a set of equations that link voltages and currents

Behavior of the device can be simulated and predicted Basic MOS model components 1. 2. Equations describing Ids (Vds) and Ids (Vgs) Parameters that link the technology being used for fabrication

Requirements of good MOS model

Good I-V characteristic accuracy Meet charge conservation requirement Correct values of small-signal quantities Good prediction for white and 1/f noise Ability to provide results even when device operation is quasi static

Ability to include all physical mechanisms for sub-micron

devices

Benchmark tests

Benchmark tests used to examine the accuracy For simple circuits unveils the problem areas for a given model

General benchmark tests that can be performed are:

DC tests Small signal tests Noise tests Frequency test

Flowchart of the operation

Fig 2 Flowchart for choosing the correct MOS model

Generation of MOS models

Generation 1

MOS 1 (LEVEL 1) **** MOS 2 (LEVEL 2) MOS 3 (LEVEL 3)

Generation 2

BSIM 1 (LEVEL 13) MODIFIED BSIM (LEVEL 28) BSIM 2 (LEVEL 39)

Generation 3

BSIM 3 (LEVEL 47) **** MOS 9 (LEVEL 50) BSIM 4 (LEVEL 54) EKV (LEVEL 55) **** BSIM3-SOI (LEVEL 59) MOS 11(LEVEL 63) ****

Generation I

Focuses on analytical expressions and extraction of parameters

Source: Kriplani, N., Transistor modeling using Advanced Circuit Simulator Technology

Fig 3 Schematic of LEVEL 1, 2 and 3 MOSFET models

MOS 1 model

Model equations simple Implements the Shichman-Hodges model Based on gradual channel approximation and square law for saturated drain current

Advantages

Can be used for preliminary circuit simulations Appropriate for long channel and uniform-doping devices

Generation II

Focus on mathematical conditioning and robust circuit simulation

Focus less on developing exact analytical models Binning concept introduced

Process of modifying the model parameters for different values of drawn channel length and width

HSPICE binning uses multiple model statements modeling a range of different lengths and widths

Generation III - BSIM 3

Model derived from research of General Electric and Intersil Enhanced version of Ids equation from LEVEL 2 model Varies from LEVEL 2 model in the area of

Substrate doping Threshold voltage Effective mobility Channel length modulation Sub-threshold current

MOS 11 model

Symmetrical, surface potential based model Provides accurate physical description of transition from weak to strong inversion

Simple parameter extraction Appropriate for digital, analog and RF design

EKV model

Physics based MOSFET model Has less than twenty intrinsic model parameters Specifically geared towards analog circuit simulation Useful for statistical modeling tasks Models available for all major circuit simulators

Overview of experiments

Goal is to show quantitative results proving that by choosing the correct model the results are improved

Hardware description language Verilog-AMS used to compare the results against the results obtained in SPICE

For simulations, HSPICE (Version: hspice-X-2005.09-SP1) from

Synopsys and Verilog-AMS (Version: IUS version 5.6) from Cadence were used

Used 4 X 336-Mhz UltraSPARC-II processors, 1.3GB of memory

and the Solaris 9 operating system for simulations

HSPICE

Analog simulator Capable of performing transient, steady state and frequency domain analysis

Capable of simulating up to 100,000 transistors HSPICE program contains four parts

Title line

Element declaration
Control commands .END

HSPICE (Contd.)

To view results from transient analysis, Avanwaves was used

Avanwaves is a point and click interface with bult-in math functions for users

Hardware description languages (HDLs)

By definition HDL is a programming language for developing executable simulation models of hardware systems

HDLs describe circuits operation and design and also have tests to verify the circuits functionality by simulation

HDLs can be used to design dedicated IC even before the actual circuit is built

The HDL that was used for simulations in this thesis was Verilog-AMS

Verilog-AMS

Supports both analog and digital component description Description in analog components is done by Verilog-A and digital components by Verilog-HDL

Has SPICE compatibility with SPICE netlist by defining:

Primitive names Parameter names Port names

Facilitates code reuse and ease of design

Verilog-AMS (Contd.)

Unique feature of this language is the possibility of interconnecting instances of Verilog HDL, Verilog-A and Verilog-AMS with their netlists in a single module

Both electrical and non-electrical models can be described in Verilog-AMS

Available HDL transistor model descriptions

Table 2 Different MOS models available

Description of experiments

In this thesis, simulations performed initially for CMOS inverter using a specific MOS model

Then the same MOS model was used in a op-amp circuit to compare the performance when different MOS models are used

Structural level of MOS is used for all simulations Three MOS models were studied MOS 1, MOS 11 and EKVMOS

CMOS inverter

Consists of one PMOS and one NMOS as shown

Fig 4 Schematic of CMOS inverter

Four terminals gate, drain, source and bulk Specific components were instantiated in Verilog-AMS like the type of transistor, transistor length, width and terminals of each transistor

Test bench consisted of applying 0 to 5V in steps of 0.1v

CMOS inverter (Contd.)

For spice simulation, a basic inverter was constructed using 0.8 technology and used level 49 BSIM v3 model

The output was observed for all these simulations by varying the W/L ratio of both PMOS and NMOS transistors

The output observed was the inverted form of the input

Results

Two types of experiments were performed for CMOS inverter

Constant supply voltage with varying transistor dimensions Constant W/L ratio (2) with varying supply voltage

Simulations
CMOS Inverter transfer characteristics Structural Model 6 5
Output Voltage (V)

CMOS Inverter transfer characteristics Structural Model 6 5

Output Voltage (V)

4 3 2 1 0 -1 0 1 2 3
Input Voltage (V) SPICE MOS 1

4 3 2 1 0

-1

3
Input Voltage (V)

SPICE

Verilog-AMS(MOS11)

CMOS Inverter transfer characteristics Structural Model 6 5

Output Voltage (V)

4 3 2 1 0 -1 0 1 2 3
Input Voltage (V) SPICE EKVMOS

Simulations--Errors
% Error Vs Input voltage (V) 120 100 80
%Error
%Error

% Error Vs Input voltage (V) 200 100 0 -100 -200 -300 -400 -500 0 1 2 3 4 5 6

60 40 20 0 -20 0 1 2 3
Input Voltage (V) MOS 1 and SPICE

-600

Input Voltage (V) MOS 11 Vs SPICE

Fig 4.4 Relative error between the MOS 1 and SPICE model (Inverter)
% Error Vs Input voltage (V) 120 100 80
%Error

Fig 4.5 Relative error between the MOS 11 and SPICE model (Inverter)

60 40 20 0 -20 0 1 2 3
Input Voltage (V) EKVMOS Vs SPICE

Fig 4.6 Relative error between the EKV and SPICE model (Inverter)

Operational amplifier

Two inputs that operate on dual DC power supply and has a high open-loop gain

On feedback, the closed-loop gain is determined by the feedback network

Fig 6 Op-amp schematics

CMOS Structure of op-amp

Source : R. Jacob Baker, Harry W.Li & David E. Boyce, CMOS Circuit Design, Layout and Simulation

Fig 7 Schematic of op-amp with W/L values

Op-amp parameters

Considered three cases

Original dimensions 75% original dimensions 50% original dimensions

Dimensions of the transistor changed only for the differential stage not the output stage

Simulations performed with 5V dc supply and ramp input given to MOS models had a sweep from -2.5V to + 2.5V

Unit step function

Source: Simon Foo, Lisa Anderson & Yoshiyasu Takefuji Analog Components for the VLSI of Neural Networks IEEE, 1990

Fig 8 Structural model of unit step function with test parameters

The value of output follows the function f(x)=0 for x <= 1 1 for x > 1

Simulations
Unit Step Function Structural Model
5 4 2 1 -3 -2 -1 0 -1 0 -2 -3 -4 -5 Input Voltage (V) 1 2 3

Unit Step Function Structural Model 6

Output Voltage (V)

Output Voltage (V)

4 2 0 -3 -2 -1 -2 -4 -6
Input Voltage (V) SPICE Verilog-AMS(MOS 11)

Verilog-AMS(MOS1)

SPICE

Unit Step Function Structural Model

5 4 3 2 1 0 -1 0 -2 -3 -4 -5
Input Voltage (V) SPICE Verilog-AMS(EKVMOS)

Output Voltage (V)

-3

-2

-1

% Error
% Error Vs Input Voltage
250 200
Error(%)

%Error Vs Input Voltage

140 120 100
Error(%)

150 100 50 0 -3 -2 -1 -50 0 1 2 3

80 60 40 20 0 -3 -2 -1 0
Input Voltage (V)

Input Voltage (V)

MOS 1 and SPICE

MOS 11 and SPICE

% Error Vs Input Voltage

104 103 102 101 100 99 98 97 96 -3 -2 -1 0
Input Voltage (V)

Error(%)

EKVMOS Vs SPICE

Linear function (Fixed threshold)

Source: Simon Foo, Lisa Anderson & Yoshiyasu Takefuji Analog Components for the VLSI of Neural Networks IEEE, 1990

Fig 9 Structural model of Linear function with test parameters

Simulations
Linear Function (Fixed Threshold) Structural Model 5 4 3 2 1 0 -1 0 -2 -3 -4 -5
Input Voltage (V) Verilog-AMS(MOS 1) SPICE

Linear Function (Fixed Threshold) Structural Model 4 3 2 1 0 -1 0 -2 -3 -4 -5 Input Voltage (V)

SPICE Verilog-AMS(MOS11)

Output Voltage (V)

Output Voltage (V)

-3

-2

-1

-3

-2

-1

Linear Function (Fixed Threshold) Structural Model 4 3 2 1 0 -1 0 -2 -3 -4 -5

Input Voltage (V) SPICE EKVMOS

Output Voltage (V)

-3

-2

-1

% Error
% Error Vs Input Voltage(V)
20 10

% Error Vs Input Voltage

250 200 150 100 50 0 -50 0 -100 -150

Error(%)

-3

-2

-1 -10 -20 -30 -40

%Error

d2-f2

-3

-2

-1

Input Voltage(V) MOS1 and SPICE

Input Voltage (V) MOS 11 and SPICE

% Error Vs Input Voltage

200 150
%Error

100 50 0 -3 -2 -1 0
Input Voltage (V)

EKVMOS and SPICE

Conclusion

Different Verilog-AMS MOS models were successfully tested in

inverters and also op-amps

Output voltages for different MOS models for both inverter and

op-amp were compared

Assumption - More accuracy and timing

advanced

MOS

models

have

better

CHANGE: Of all MOS models that were used, MOS 1 is the

most accurate model, matching closely with the SPICE values

Conclusion (Contd.)

MOS 11 and EKVMOS models available for use in this thesis dont represent the complete models

Verilog-AMS models currently available not mature enough to get results as expected

Future work

To improve accuracy, improve the current models Open source library of models can be developed

THANK YOU

Questions??

Supplementary Slides

MOS 2 model (Generation 1, Level II)

Geometry based model Advantages

Takes into account velocity saturation, mobility degradation and DIBL

Disadvantages

Not accurate for models with submicron geometries Has convergence problems Slower

MOS 3 model (Level III)

Has semi-empirical parameters to model short channel effects

Uses measured data to determine its main parameters Works well for channel lengths less than 1m More accurate than LEVEL 1 and LEVEL 2 models Advantages

Simple Operational reliability

Disadvantages

Abrupt change from linear to saturation region Poor fit of data

BSIM 1 (Level ???)

Same as LEVEL 2 model with the following exceptions

Doesnt have narrow width effects No short-channel effects Model parameter TPG defaults to zero for aluminum gate and for other levels, it defaults to one

Value of VT0 is computed using this parameter

BSIM 2 (Level XIII)

Two modes of operation

Enhancement Depletion

If the mode parameter ZENH value is 1, then its the enhancement model else its the depletion model

HSPICE 28 (Level ???)

Model binning can be accomplished Model parameter is set empirically Geared towards analog design

BSIM 4 (Level ???)

Enhanced version of BSIM3 Accounts for the physical effects when the 100nm regime is reached

Accurate model of intrinsic input impedance for analog, digital and RF applications

Accurate model for induced gate noise and thermal noise

MOS 9 model (Level ???)

Physics based model specifically geared towards analog simulation developed by Philips

Very good description of electrical characteristics for all regions of transistor operation

Even using one parameter set, behavior of the model over a wide range of lengths and widths

Appropriate not only for circuit design, process technology but also in CAD tool development