EECE579: Digital Design Flows

Usman Ahmed Dept. of ECE University of British Columbia

Implementing Digital Circuits

Digital Circuit Implementation Approaches

Custom

Semicustom

Cell-based

Array-based

Standard Cells Compiled Cells

Macro Cells

Gate Arrays Structured ASICs

FPGA's

Implementing Logic Circuits

Design Capture Behavioral

Design Iteration

HDL Pre-Layout Simulation Structural Logic Synthesis

Floorplanning Post-Layout Simulation Circuit Extraction Placement Routing Physical

Tape-out

Standard Cell Design

Library of cells that implement different gates
Cells can have different width but all cells have same height (hence Standard Cells) Many variants of the same cell

Standard Cell Design

Logic Synthesis Transform the HDL description into library cells
Placement Where to place a cell ? Routing Connect the placed cells.

Standard Cell Design

Optimizations: Gate Resizing Buffer Insertion In-place Re-synthesis

Standard Cell Design: An Example

Standard Cell Design

Routing channel can be narrowed if more interconnect layers are available

Standard Cell Design: New Generation

Cell-structure hidden under interconnect layers

Standard Cell Design: Summary

Used only for the highspeed or low-power applications
Very expensive, and time consuming

(> $2M just for the mask costs) Very high re-spin cost

FPGAs
FPGA: Field-Programmable Gate Array

Circuit Description

Expensive Chip Manufacturing

Gate Array

Whats Inside an FPGA?

Logic Blocks - used to implement

logic
- lookup tables and flip-flops Altera: LABs Xilinx: CLBs

Whats Inside an FPGA?

I/O Blocks - interface off-chip - can usually support many I/O Standards

Whats Inside an FPGA?

Logic Block Connection Block Switch Block Routing Track (Horizontal) Routing Channel (Vertical)

TILE

Logic Block:
Basic Logic Gate: Lookup-Table

Inputs
Bit-Stream Function of each lookup table can be configured by shifting in bit-stream.

Logic Clusters

Local Interconnect
D Q

Several lookup tables are grouped into clusters - Typically 8 to 10 lookup tables per cluster Connections between lookup tables in the same cluster are fast Connections between lookup tables in different clusters are slow

D Q

D Q

Whats Inside an FPGA?

Logic Block Connection Block Switch Block Routing Track (Horizontal) Routing Channel (Vertical)

Reconfigurable Logic:
Connect Logic Blocks using Fixed Metal Tracks and Programmable Switches

Reconfigurable Logic:
Connect Logic Blocks using Fixed Metal Tracks and Programmable Switches

Implementing Systems in an FPGA

FPGA Fabric Embedded memories
Embedded PowerPC

Hardwired multipliers

Xilinx Vertex-II Pro

High-speed I/O

Advantages of FPGAs:
"Instant Manufacturability": reduces time to market Cheaper for small volumes because you dont need to pay for fabrication
means you dont need to be a big company to make a chip

Relaxes Designers -> relaxed designers live longer!

Disadvantages of FPGAs:
Slower than custom or standard cell based chips Cannot get as much circuitry on a single chip Today: ~ 1M gates is the best you can do ~ 200 MHz is about as fast as you can get
For large volumes, it can be more expensive than gate arrays and custom chips

Structured ASICs
Combines good features of FPGAs and Standard Cell ASICs

- Standard Cell ASIC

All the layers are customized for a circuit
Interconnect Layers

- Structured ASIC
Some layers are generalized while a few layers are customized for a circuit

Transistors

- FPGA
All the layers are generalized for any circuit

Logic Blocks
Choices
Fine Grained
Basic gates: NAND, NOR, XOR, FF etc.

Medium Grained
Lookup Tables

Coarse Grained
Multi-input, Multi-output blocks (e.g., PLAs)

Configurability
SRAM cells Vias
Lower Level (e.g., between M1 and M2) Upper Level (Via stacks brought up to the configurable layers)

Routing Fabrics
Metal and Via Programmable
More flexibility, more efficiency Employed in most structured ASIC offerings

Via Programmable
Regular, easy to manufacture Metal is fixed and every segment may not be fully utilizable,
Can be Inefficient

Design Flows

Design Flows

Design Flows

Design Flows

Design Flows

Implementing Logic Circuits

Design Capture Behavioral

Design Iteration

HDL Pre-Layout Simulation Structural Logic Synthesis

Floorplanning Post-Layout Simulation Circuit Extraction Placement Routing Physical

Tape-out