PDH and SDH 2

Intersymbol interference in the Detection process (a) typical baseband digital system and (b) equivalent model
X1 X2 Xk T Transmitting filter T X3 Noise channel Receiving filter Detector

Xk '

(a)

X1 X2 Xk T H(f)

pulse 1

pulse 2

h(t)
X3 T

Detector

Xk '

(b)

Nyquist channels for zero ISI (A) Rectangular system Transfer function H(f) (B) Received Pulse Shape h(t)= Sin (t/T)
h(t)
H(f)

-1/2T

t
1/2T

-T

(a)

(b)

Sampling with a jitter reference clock

A jitter passed along chain of N repeaters due to a sudden pattern change at time t=T

output jitter amplitude

slope= Bd

N=3 N=2 N=1

Equivalent input jitter amplitude

Time d

t=T

Time

t=T+N/B

The normalized power density spectra for a route containing 1,10 and 100 repeaters
N=100 40

0dB =jitter introduced at each regenerator

N=10

dB
20

N=1

10-2

10-1

f/B

SAMPLING WITH A JITTERY REFERENCE CLOCK

receiving signal level [mV] threshold level jitter free data crossing Jitter free data crossing (nominal) time
JDP

data transition peak jitter

position of jitter free reference clock

JCP

JCP

Ts/2

Ts/2

Ts= nominal symbol duration

JSCP>Ts/2

JSCP>Ts/2

BINARY EYE AND ASSOCIATED CLOCK WITH JITTER

Eye width W Information pulse D D Eye jitter limit

Timing interrogation pulse (extracted clock) d d

clock jitter limit

JITTER FREE EYE PATTERN

Received Signal level (mV)

Threshold level

Time Jitter free data crossing (nominal)

Jitter free data crossing

Position of jitter free reference clock

Ts/2

Ts/2

Ts = symbol duration

Table- FCC-Authorized Frequency Bands and the North American Digital Hierarchy

FCC regulations

Digital Hierarchy

Authorized Frequency Band (GHz)

Allowable Bandwidth (MHz)

Minimum capacity of Encoded Voice Channels (N)

Corresponding PCM Bit rate, No. of 64Kbps (In Mbps)

Closet Hierarchy Level and Bit Rate (Mbps)

No. of PCM channels in Hierarchy

Efficiency

2.110-2.130

3.5

96

6.144

DS-2 6.312 DS-2 6.312

96

1.8

2.160-2.180

3.5

96

6.144

96

1.8

3.770-4.200

20

1152

73.728

2 DS-2 Approx 90 2 DS-2 Approx 90

1344

4.5

5.925-6.425

30

1152

73.728

1344

2.25

Table-2 CCIR Frequency Allocations

FDM

Digital CCIR Rec.

Frequency Band (GHz)

Frequency Range (MHz)

1700-1900 1900-2100 2100-2300 2500-2700 1700-2100 or 1900-2300

Channel Spacing (MHz)

Channel Capacity

Band Capacity*

Channel Capacity

Band Capacity

14

60,120,300

__

__

283-2

29

600-1800

__

__

382-2

3700-4200

29 40 29.65 40 20

600-1800 1260 1800 2700 1260

6 6 8 8 16

__ __ __ __ __

__ __ __ __ __

382-2 382-2 383-1 384-2 384-2

5925-6425 6430-7110

Table 3- CCIR Frequency Allocations

FDM

DIGITAL

Frequency Band (GHz)

7

Frequency Range (MHz)

7425-7725

Channel Spacing (MHz)

7/14

Channel Capacity

Band Capacity

Channel Capacity

Band Capacity*

CCIR Rec

60, 120/300

20

__

__

385

8200-8500 7725-8275

11662 29.65

960 1800

6 8

__ __

__ __

386-1 386-1

11

10700-11700

40

1800

12

MEDIUM (480-960)

11

387-1

13

1275013250

28 14 35

960 300 __

8 Additional __

960# 240 720

8 Additional

497 497 497

*Go and return channels

# using 480 channels on both polarizations

Analogue Microwave Transmitter

Antenna

voice data video

BB

IF

RF

FDM

Frequency Mod

Mixer

RF stage

RF Local oscilattor

Digital Microwave Transmitter

Antenna

voice data video

BB

IF

RF

TDM

PSK or QAM Mod

Mixer

RF stage

RF Local oscilattor

Analogue Microwave Radio Receiver

antenna

RF

IF

BB

voice

RF stage

Frequency Mixer Demod

FDM MUX

data video

Local oscillator

Digital Microwave Radio Receiver

antenna

RF

IF

BB

voice

RF stage

PSK or QAM Mixer

TDM

data video

Demod

MUX

Local
oscillator

Regenerative Repeater

RF

IF

BB

BB

IF

RF

Down Converter

DeMod

Pulse Restoration

MOD

UP Converter

A Block Encoder

(n,k) FEC encoder

n=K+r

K= message bits r = check bits n = code words

Concatenated Code

TX Outer Encoder Input Data Inner Encoder Link Inner Decoder Outer Decoder

RX

Output Data

Voltage

ASK
t

FSK t

PSK t

BPSK Modulator (Ring Modulator)

D1

D3

D4

or
Phase state

D2 Phase state 1 0 Baseband input

or

Baseband

MOD
Space diagram

carrier

Phase state when Baseband signal is 0 (out of phase)

Phase state when Baseband signal is 1 (inphase)

Baseband Input 1 0

Diode D1,D2 short D3,D4 open D1,D2 open D3,D4 short

Mod Output In-phase

Out of phase

4 QPSK Modulator
Symbol rate fb/2

180 0
Serial to parallel converter Baseband data input Tx osc: Phase shift

90 90

BPF

IF

11 01

270
Symbol rate fb/2

Q
00

10

4 QPSK Demodulator
I LPF

Threshold Comp

0
IF Power Splitter Carrier recovery Symbol timing Phase splitter Recovery STR Parallel tp serial converter

Output data

90

LPF Q

Threshold Comp

8 PSK Modulator
2 level to 4 level converter DSB-SC Mod

Fb/3

Data distributor Baseband input

Fb/3

Local osc: 90

BPF IF

Inverter Fb/3 2 level to 4 level converter

DSB-SC Mod

Single state space diagram of 8 PSK Modulator

a amplitude state of the a vector b amplitude state of the b vector

/4 DQPSK Modulator and its Signal Constellation

/2 3/4 /4

3/2 0 /2

2 0

Baseband input

5/4 3/2

7/4

+
/2 I /4

/4 DQPSK Modulator

IF

10 Phase Decision Threshold

00 Vector transmitted error free

01 Vector transmitted erroneous

Error region

E1

/m

E N
=0 noise free ref: vector

b 0

C BW N f
b

11 E2

-/m

01

E N

b 0

C BW N f
b

Eb= Average energy of a bit fb = Transmitted Bit rate (1/Tb) Tb= Unit Bit Duration C= Average Carrier Power N0= Noise Power Spectral Density that is average Noise Power in 1KHz Bandwidth BW = Noise Bandwidth of Receiver

Differential Encoder For Differential Phase Shift Keying Modulator

Input data

Modulo 2 Adder

Encoded Data out

Delay Tb

DPSK is often used instead of BPSK because DPAK receiver does not require a carrier synchronizer circuit.

/4 DQPSK Demodulator
T 0

dt

Sampler b1

Delay Tb
90 Phase shift

Synchronizer

T 0

b2 Sampler

dt

01
01 00

11

00

10

11
10 M = 4, =0 M = 4, =/4

8 PSK High Speed Modulator

fb fb fb

High Speed Digital Communicate Multiplexer

Analog BPF
Band Limited 8PSK Output

45

90 135 180 225 270 315

DIGITAL PHASE SHIFTER

Digital IF Local Oscillator

16 State QAM Modulator

DSB-SC AM MOD

2 to L level Converter
fb/2

Pre-Mod LPF
fb/2 . 1/log2 L 0

Data
fb/2

Local osc:
fb/2 . 1/log2 L

Phase Splitter
90

IF A P

BPF

2 to L level Converter

Pre-Mod LPF
DSB-SC AM MOD

M-Ary QAM or M-Ary PSK Demodulator

Vn1 Vn2 l O

LPF

g I

Vn(L-1)

S
Amp

C R 90 90

T R

X2 data combiner

Data Output fb

LPF

L to 2 level converter same as design for I ch

MSK Minimum Shift Keying

1
0

0
T

NRZ data

Fsk modulator

Fsk Modulated output

carrier

Gaussian Minimum Shift Keying

Gaussian Filter
Input Binary Data

MSK MOD
GMSK Output

Front view of uncovered DM7G-1000

DSC 1(VF/DGTL)

B-U/U-B(WS)

SVLGC2 or 3

MODEM

SVLGC1

MODEM

RX

RX

PS

TX

TX

PS

No.1

No.2

No.1

No.2

No.1

No.2

No.1

No.2

BR NTWK [Branching network]

-DSPL is removed-

Rear Panel DM7G-1000

FG
G : positive supply wire (Grounded) -V: Negative supply wire(24/-48V) WS OUT WS IN No.1 No.2
EQP ALM 2

-V

G
EXT CONT

-V
EXT SV EQP ALM 1

B IN/OUT 1
WS IN/OUT

EXL

**

EXT

ALM

B IN/OUT 2

**
VF/DGTL EXT TEL

RF channel Arrangement
f0= 7575 MHz
7425 MHz 300 MHz 7725 MHz

161 MHz 56 MHz 9 17

1'

V(H) H(V)

9'

17'

13

5'

13'

Lower half of the band : fn = f0 -154+ 7n Upper half of the band : fn = f0 +7+ 7n Where n = 1,2,3,4,----20

Main Signal Flow Diagram of Radio Equipment

B-U/U-B MODEM (No.1) TX (No.1) IFA MIX PLO HPA Branching Network

TDP
B IN x 16 B-U/TDP 1*

MOD
OSC

RX (No.1) RDP optional WS IN 3* TVE DEM OSC IFA MIX PLO LNA

RF IN/OUT

(ws)
WS OUT MODEM No.(2) TX (No.2) IFA MIX PLO HPA

TDP
2* B OUTx 16 U-B/RSW RDP 4*

MOD
OSC

RX (No.2) TVE DEM OSC IFA MIX PLO LNA

B-U = Bipolar to Unipolar TDP = Transmit Data Processing RDP = Receive Data Processing PLO = Phase Locked Oscillator TVE = Transversal Equalizer IFA = IF Amplifier MIX = Mixer HPA = High Power Amplifier LNA = Low Noise Amplifier WS = Wayside Signal MOD = Modulator DEM = Demodulator

Auxiliary Signal flow (AS-30 EXL)

DSC 1

*** At mount of SV Logic 2 unit , two serial lines.

VF/DGTL (user ch) Other AS-30EXLs

VF/ DGTL
Optional

DSC INTF (MUX/DMUX) (STF/DSTF)

*1 *2 *3 *4

At mount of SV Logic 3 unit, parallel relay contacts.

DIG CON TEL/ BR NET

DSPL 3

repeat/branch

Handset
spk

OW TEL branch SV Logic 1

RADIO Multi-LVL monitor Alarm 2-level

DRV PIU

DISPLAY

Operation

SV Logic 2 or 3 (Optional) MPU MPU

30EXL INTF

DI

COM. RAM

INTF

***
Station Supervisory Control

RSW Control

SW CONT

EXT .SV /EXT .CONT

AS = Auxiliary signal MPU = Microprocessor Unit DRV = Driver PIU = Peripheral Interface Unit STF/DSTF = Stuffing and Destuffing SPK = Speaker

Protection Switching for Twin-path System

B-U/U-B No.1 Modem No.1 Modem MOD TX B-U/U-B

RX

DEM

U-SW

band B-U Input

No.2 Modem MOD TX RX

No.2 Modem DEM

U-B

DSC

DSC O Input

Layout of functional section of DSPL-3

COMMON TEL
DISP OFF

SUPERVISORY
Eqp No.

TALK

Sys sv alm alm norm

1 2 3

EQP ALM

ALM/STATUS

MONITOR
8

No.1 No.2
T ALM R ALM CH ALM PS ALM WS ALM SV FL AIS REC AIS SEND MAINT AL-RA No. SEL 1 2

RSW INI OP

EXT SV NG 1 2 3 4 5 9 10 11 12 13

No.1
COUNT EC BER ES SES DM PT EXEC EXEC ON ON AUTO

No.2

T LVL R LVL + 5.3V +10V -10/-5.5V ITEM SEL DC IN[V]

AL-RA

VOL

BZ off

4 5 6
MASTER

No.1

14
15 16

IND CHK

BZ RST

HST RST

7 8

No.2

7 8

(SEC)