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Outline
Part 1 Programmable Logic CPLD FPGA
Architecture Examples Features Vendors and Devices
Part 2 VHDL
Introduction Examples
Design Flow
Entry Methods Simulation Synthesis Place & Route
coffee break
Introduction to VHDL
VHDL Language
Hardware Description Language (HDL)
High-level language for to model, simulate, and synthesize digital circuits and systems.
History
1980: US Department of Defense Very High Speed Integrated Circuit program (VHSIC) 1987: Institute of Electrical and Electronics Engineers ratifies IEEE Standard 1076 (VHDL87) 1993: VHDL language was revised and updated
At CERN VHDL is mostly used for FPGA design Many tools accept both Verilog and VHDL
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Terminology
Behavioral modeling
Describes the functionality of a component/system For the purpose of simulation and synthesis
Structural modeling
A component is described by the interconnection of lower level components/primitives For the purpose of synthesis and simulation
Synthesis:
Translating the HDL code into a circuit, which is then optimized
Each circuit primitive can be described in VHDL and used as the basis for describing more complex circuits.
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AND
E F W
It is possible to design circuits from logic gates in this way For design entry it is preferable to use other VHDL structures that allow circuit descriptions at a higher level of abstraction
NOR
Interface
A(0)
Z(0)
Functionality
architecture when_else of decoder is begin Z <= "0001" when A = "00" else "0010" when A = "01" else "0100" when A = "10" else "1000" when A = "11" else "XXXX"; end architecture when_else;
A(1..0) 0 0 0 1 0 0
Z(3..0) 0 0 0 1 1 0
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1
0
1
0
1
1
0
0
0
0
0
4-to-1 Multiplexer
entity mux is port ( a, b, c, d: in std_logic; s: in std_logic_vector(1 downto 0); y: out std_logic); end entity mux;
a
b y c d
architecture mux1 of mux is begin process (a, b, c, d, s) begin case s is when "00 => y <= a; when "01" => y <= b; when "10" => y <= c; when "11" => y <= d; end case; end process; end architecture mux1;
S(1) S(0)
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Binary Counter
entity counter is generic (n : integer := 4); port ( clk : in std_logic; reset: in std_logic; count: out std_logic_vector(n-1 downto 0) ); use ieee.numeric_std.all; end entity counter; architecture binary of counter is begin process (clk, reset) variable cnt : unsigned(n-1 downto 0); begin if reset = '1' then -- async reset cnt := (others => '0'); elsif rising_edge(clk) then cnt := cnt + 1; end if; count <= std_logic_vector(cnt); end process; end architecture binary;
This example is not explicit on the primitives that are to be used to construct the circuit. The + operator is used to indicate the increment operation.
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State Machine
If a trigger signal is received, will stretch it to 2 cycles and wait for accept signal
entity trigger is port ( clk, reset: in trigger, accept : in active: out end entity trigger; std_logic; std_logic; std_logic);
curr_state
clk
architecture rtl of trigger is type state_type is (s0, s1, s2); signal cur_state, next_state: state_type; begin registers: process (clk, reset) begin if (reset='1') then cur_state <= s0; elsif rising_edge(clk) then cur_state <= next_state; end if; end process;
trigger
Output Logic
accept
reset
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S0
trigger
S1
accept
S2
clk curr_state
Output Logic
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RTL Simulation
Functional Simulation Verify Logic Model & Data Flow (No Timing Delays)
LE
MEM I/O
Synthesis
Translate Design into Device Specific Primitives Optimization to Meet Required Area & Performance Constraints
Timing Analysis
- Verify Performance Specifications Were Met - Static Timing Analysis
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Block Diagram
Hierarchical design methods:
top-down bottom-up
Contents of a block can be any type of design unit Top-level block diagram:
Partitioning of the design Connections between the underlying HDL design units
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State Diagram
Bubble diagram
States
Conditions
Transitions
Outputs
Truth Table
Normally used to describe combinatorial logic Can also be used for sequential circuits (e.g. state machines)
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Timing simulation:
simulate after place and routing detailed timing
Synthesis
Place & Route
Simulation
Program device & test
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Simulation Results
Example of simulation waveforms. Test vectors are normally defined in a VHDL unit (testbench)
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RTL Synthesis
Input is RTL code Compilation & translation
Generates technology independent netlist RTL schematic (HDL code analysis)
Design Entry Simulation
Technology mapping
Mapping to technology specific structures:
Look-up tables (LUT) Registers RAM/ROM DSP blocks Other device specific components/features
Synthesis
Place & Route
Simulation
Program device & test
Logic optimization
Implementation analysis (technology view)
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Functions
Place-and-route Constraints editor Backannotated netlist for timing simulation Configuration bitstream
Synthesis
Place & Route
Simulation
Program device & test
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Logic synthesis Place & route Simulation Timing & power analysis Create netlist for timing simulation Device programming
Accelerate design entry and verification Pre-optimized for FPGA vendor architecture Provided at no cost by the FPGA vendor to optimize performance Instantiate block in the design:
Makes HDL code technology dependent
IP cores:
More complex blocks: PCI-X interface, CPU, etc. Some are provided by the FPGA vendor IP cores from third party suppliers cost money Evaluation before buying usually possible
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Macro Example
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Simulation
Cadence NCsim
Synthesis
Synplify (Synplify) Leonardo (Mentor) FPGA fitter built-in
Altera NIOS-II evaluation kit Programming cables for FPGAs are available for short-term loan Tool usage:
Windows PC tools can be installed from: \\dsy-srv4\caeprogs CAE Sun cluster: login to dsy-srv
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Other resources:
Mailing list for electronics designers at CERN: cern-electronics@cern.ch Digital CAE User's Group (DUG): http://wwwinfo.cern.ch/ce/dc/DUG/DUG_home.html
Technical Training:
Visual HDL course Introduction to VHDL & using the ncvhdl simulator from Cadence http://cern.ch/humanresources/Training/tech/electronics/te_elec.asp
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Bibliography
Acknowledgements:
E. van der Bij (CERN), J. Christiansen (CERN)
Further reading:
FPGA vendor sites:
http://www.altera.com http://www.xilinx.com
P. Alfke (Xilinx), Field Programmable Gate Arrays in 2004, Proceedings of LECC2004. M. Zwolinski, Digital System Design with VHDL - 2nd Ed., Prentice-Hall, 2000, (Chap. 4 & 6)
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