Simulation of Switching Converters

Time
0s 1ms 2ms 3ms 4ms 5ms 6ms 7ms 8ms 9ms 10ms
V(out) AVG (V(out))
0V
20V
40V
V(error) AVG (V(error))
-20V
0V
20V
V(control) AVG (V(control))
0V
10V
20V
SEL>>
AVG (V(out))
V(out)
V(error)
AVG(V(error))
V(control)
AVG(V(control))
Chapter 9
Simulation
of
Switching Converters
Power switching converters Simulation of switching converters 2
Overview
PSpice
PSpice Simulations using .CIR
PSpice Simulations using schematics entry
PSpice Simulations Using Behavioral Modeling
PSpice simulations using vendor models
Small-signal analysis of switching converters
Creating capture symbols for PSpice simulation
Solving convergence problems
Matlab
Simulink
An Ideal Open-Loop Buck Converter
L
O
10mH
C
O
R
V
PWM
+
-
1 2
0
100F
5O
Open-loop buck converter simulation
* SWITCHING FREQUENCY = 1 KHZ ; DUTY CYCLE = 50%
VPWM 1 0 PULSE(0 10 0 1US 1US 0.5MS 1MS)
* PULSE PWM SOURCE: PULSED VOLTAGE = 10 V, RISE TIME = 1 US,
* FALL TIME = 1 US, PULSE WIDTH = 500 US, PERIOD = 1 MS.
L0 1 2 10M
C0 2 0 100U
RL 2 0 5
.TRAN 50US 20MS
.OPTION ITL5=0
.PROBE
.END
Time
0s 5ms 10ms 15ms 20ms
V1(RL) I(C0) I(L0)
-4.0
0
4.0
8.0
I(C0)
I(L0)
V1(RL)
Time
I(C0) I(L0) V(2)
-2.0
0
2.0
4.0
6.0
I(CO)
I(LO)
V(2)
L = 50 mH
Time
V(2) I(LO) I(CO)
0
2.0
4.0
6.0
-1.0
V(C2)
I(LO)
I(CO)
L = 5 mH
Time
V(2) I(LO) I(CO)
-2
0
2
4
6
8
10
V(2)
I(LO)
I(CO)
L = 1.25 mH
Time
V(2) I(LO) I(CO)
-2.0
0
2.0
4.0
6.0
8.0
I(CO)
I(LO)
V(2)
L = 10 mH
and
C = 500 uF
Time
V(2) I(LO) I(CO)
-5
0
5
10
I(CO)
I(LO)
V(2)
L = 1.25 mH
and
C = 500 uF
S
R
on
N
N
N
+
c
+
N
-
-
c
Voltage-controlled switch
S<name> N+ N- NC+ NC- SNAME
.MODEL SNAME VSWITCH (RON=0.01 ROFF=1E+7 VON=0.7 VOFF=0)
Current-controlled switch
R
on
W
N
-
+
N
N
V
W<name> N+ N- VN WNAME
.MODEL WNAME ISWITCH (RON=0.01 ROFF=1E+7 ION=0.1 IOFF=0)
Buck Converter with an Ideal Switch
CO
100uf
LO
10mH
1
S1
VPWM
DFW
0
VS 10V R
5ohms
2
RSX
3
OPEN-LOOP BUCK CONVERTER WITH AN IDEAL SWITCH
* SWITCHING FREQUENCY = 1 KHZ ; DUTY CYCLE = 50%
VS 1 0 10.0
VPWM 100 101 PULSE(0 1 0 1US 1US 500US 1MS)
S1 1 2 100 101 SX
RSX 100 0 10G
DFW 0 2 D1
L0 2 3 10M
C0 3 0 100U
RL 3 0 5
.MODEL SX VSWITCH (RON=0.01 ROFF=1E+7 VON=1 VOFF=0)
.MODEL D1 D
.TRAN 0.05MS 20MS
.PROBE
.END
Time
V(3) I(LO) I(CO)
0
2.0
4.0
6.0
-1.0
I(CO)
I(LO)
V(3)
Time
15.0ms 15.5ms 16.0ms 16.5ms 17.0ms 17.5ms 18.0ms
V(3) 20* I(CO)
0
5.0
-3.0
I(CO)*20
V(3)
L0 2 3 100U IC=1
C0 3 0 IC=5
.TRAN 2NS 200NS UIC
Using Initial Conditions IC
Time
V(3) I(LO) I(CO)
0
2.0
4.0
6.0
-1.0
I(CO)
I(LO)
V(3)
PSpice Simulations using schematics
entry
Boost converter
+
-
+
-
S
1
S
VON = 1.0V
VOFF = 0.0V
ROFF = 1e6
RON = 1.0
pwm
D
break
D
1
0
V
2 TD = 0
TF = 1n
PW = 0.5m
PER = 1m
V1 = 0
TR = 1n
V2 = 1 R1 C
1
V
1
10V
dc
out
L
1
10mH
20O
+
-
100F
entry
Time
0s 5ms 10ms 15ms 20ms 25ms 30ms
V(out)
5V
10V
15V
20V
25V
entry
Time
I(L
1
) I(C
1
)
-2.0A
-1.0A
0A
1.0A
2.0A
3.0A
I(C
1
)
I(L
1
)
PSpice Simulations Using
Behavioral Modeling
ABM.OLB part library
Control system parts

PSpice-equivalent parts
PSpice-equivalent parts
Operators in ABM expressions
Operators in ABM expressions
Functions in arithmetic
expressions
Functions in arithmetic
expressions
Examples of ABM blocks use
PARAMETERS:
PI = 3.141592654
freq = 1k
3*sin (2*PI*freq*TIME)
sine
ABM and PARAM
control
3*V (sine)
Node voltages can be accessed from ABM blocks
rms
sine
If (TIME<=0,0,SQRT(SDT(PWR(V(%IN),2))/TIME))
RMS meter
If(argument,then,else)
If (TIME<=0, 0, SQRT(SDT(PWR(V(%IN),2))/TIME))
control
pwm
0
If (V(%IN1) > V(%IN2),1,0)
V
4
triangular
TD = 0
TF = 1u
PW = 1n
PER = 2u
V1 = -10
TR = 1u
V2 = 10
PWM modulator
Sin (2*PI*100k*ABS(V(%IN)) * TIME)
VCO triangular
VCO implementation with ABM1
PSpice Simulations Using Control
Blocks
control
0
pwm
triangular
V
4
TD = 0
TF = 0.5m
PW = 1n
PER = 1m
V1 = -10
TR = 0.5m
V2 = 10
100k
10
0
PWM modulator with control blocks
Blocks
0
OpAmp
V
4
1V
ac
0V
dc
50
50 + s IN OUT
PARAMETERS:
V
cc
= +12
V
EE
= 0
0
0
{V
cc
}
{V
EE
}
In-
0
In+
R
2
10Meg
100k
R
1
10Meg
Model of an operational amplifier
Blocks
Frequency
10mHz 1.0Hz 100Hz 10KHz 1.0MHz 100MHz 1.0mHz
P(V(OPAMP))
-100d
-50d
0d
DB(V(OPAMP))
-50
0
50
100
SEL>>
Open loop frequency response
Blocks
V
4
1V
ac
0V
dc
R
3
10k
OpAmp
0
R
2
10Meg
R
1
10Meg
0
In-
R
4
1k
50
50 + s IN OUT
In+
0
PARAMETERS:
V
cc
= +12
V
EE
= 0
100k
{V
cc
}
{V
EE
}
0
Closed loop amplifier
Blocks
Frequency
10mHz 1.0Hz 100Hz 10KHz 1.0MHz 100MHz 1.0mHz
P(V(OPAMP))
-100d
-50d
0d
SEL>>
DB(V(OPAMP))
-50
0
50
Closed loop frequency response
Voltage mode PWM boost
converter
Error amplifier
3
C
1
0
0
1Meg
1Meg+s
pwm_out
If (V(%IN1) > V (%IN2),1,0)
control
5
D
break
D
1
12
-12
V
ref
out
saw
V
1
10V
dc
+
-
+
-
S
1
S
VON = 1.0V
VOFF = 0.0V
ROFF = 1e6
RON = 0.05
error
R
2
1
pwm
sense
V
4
TD = 0
TF = 1n
PW = 1n
PER = 1m
V1 = 0
TR = 999u
V2 = 10
PWM
modulator
R
1
0
L
1
10mH
-
+
+
-
E
1
E
GAIN = 0.25
20
100F
+
-
Voltage mode PWM boost
converter
Time
V(out) AVG (V(out))
0V
20V
40V
V(error) AVG (V(error))
-20V
0V
20V
V(control) AVG (V(control))
0V
10V
20V
SEL>>
AVG (V(out))
V(out)
V(error)
AVG (V(error))
V(control)
AVG(V(control))
PSpice simulations using vendor
models
TL084
+
-
V
+
V
-
D
1
MUR420
sense
L
1
10mH
IC = 0
R
7
1
0
0
pwm_out
-15
saw
R
6
100
+15
V
ref
out
+15
R
3
100k
R
5
3k
R
4
1k
V
4
TD = 0
TF = 1n
PW = 1n
PER = 1m
V1 = 0
TR = 999u
V2 = 10
pwm
R
2
300k
R
8
300
PWM modulator
5
control
V
1
10V
dc
Error amplifier
C
1
100uF
LM311
+
-
G
V
+
V
-
B/S
B
R
1
20
0
X
2
MTP15N05E/MC
ESR
10m
-15
+
-
.TRAN 0 30m 0 0.1u
.OPTIONS STEPGMIN
.OPTIONS ABSTOL= 10p
.OPTIONS ITL1= 400
.OPTIONS ITL4= 500
.OPTIONS RELTOL= 0.01
.OPTIONS VNTOL= 10u
PSpice simulations using vendor
models
Time
V(out)
0V
10V
20V
SEL>>
V(control)
4.8V
5.0V
5.2V
I(L
1
)
0A
2.0A
4.0A
Vorperian models for PSpice
**** VMSSCCM ****
* Small signal continuous conduction voltage mode model
* Params: RMPHITE --> External ramp height
* D --> Duty cycle
* Ic --> Current flowing from terminal C
* Vap --> Voltage across terminal A P
* Rsw --> Switch on resistance
* Rd --> diode on resistance
* Rm --> which models the base storage effects
* Re --> models ripple across esr of cap
* Pins control voltage --
* common -------- |
* passive----- | |
* active -- | | |
.subckt VMSSCCM A P C VC Params: RMPHITE=2 D=0.4 IC=1 VAP=20
+ Rsw=1e-6 Rd=1e-6 Re=1e-6 Rm=1e-6
efm 4 0 value ={v(Vc)/rmphite}
e2 A 6 value={v(0,4)*Vap/d}
g1 A P value={v(4)*IC}
gxfr 6 P VALUE={I(vms)*D}
exfr 9 P VALUE={V(6,P)*D}
vms 9 8 0
rd 8 C {d*rd+(1-d)*rsw+d*(1-d)*re+rm}
rope 4 0 1g
rgnd 0 P 1g
.ends
Small-signal analysis of switching
converters
R
20
0
U7
VMSSCCM
D = 0.5
IC = -1.84
RD = 1e-6
RE = 10m
RM = 1e-6
RMPHITE = 10
RSW = 10m
VAP = -17.6
1
3
2
4
A
C
P
V
C
R
s1
300k
out
R
s
1
R
esr
10m
V
1
10V
dc
0
L
1
10mH
IC = 0
R
s2
100k
sense
V
4
1V
ac
0V
dc
C
out
100uF
IC = 0
+
-
Small-signal AC analysis
converters
Time
V(OUT)
0V
10V
20V
SEL>>
I(L
1
)
0A
1.0A
2.0A
3.0A
converters
Frequency
1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz
P(V(OUT))
-300d
-200d
-100d
-0d
DB(V(OUT))
-80
-40
0
40
SEL>>
Open-loop transfer function
converters
U7
VMSSCCM
D = 0.5
IC = -1.84
RD = 1e-6
RE = 10m
RM = 1e-6
RMPHITE = 10
RSW = 10m
VAP = -17.6
1
3
2
4
A
C
P
V
C
R
s2
100k
R
esr
10m
0
V
4
1V
ac
10V
dc
L
1
10mH
IC = 0
R
s
1
R
20
sense
out
C
out
100uF
IC = 0
R
s1
300k
0
Input impedance
converters
Frequency
DB(V(V4:+)/I(V4))
0
20
40
60
80
100
Input
impedance
converters
Output impedance
sense 0
U7
VMSSCCM
D = 0.5
IC = -1.84
RD = 1e-6
RE = 10m
RM = 1e-6
RMPHITE = 10
RSW = 10m
VAP = -17.6
1
3
2
4
A
C
P
V
C
L
1
10mH
IC = 0
R
esr
10m
0
out
R
s2
100k
V
4
1V
ac
10V
dc
R
20
R
s
1
V
5
10V
dc
R
s1
300k
C
out
100uF
IC = 0
+
-
converters
Output impedance
Frequency
DB(V(V4:+)/I(V4))
-40
-20
0
20
40
converters
L
1
10mH
IC = 0
R
s
1
R
s1
300k
U7
VMSSCCM
D = 0.5
IC = -1.84
RD = 1e-6
RE = 10m
RM = 1e-6
RMPHITE = 10
RSW = 10m
VAP = -17.6
1
3
2
4
A
C
P
V
C
R
s2
100k
V
1
10V
dc
sense
0
0
V
4
TD = 20m
TF = 1n
PW = 50m
PER = 50m
V1 = 1.2
TR = 1n
V2 = 1.5
C
out
100uF
IC = 0
R
esr
10m
R
20
out
+
-
Small-signal transient analysis
converters
Small-signal transient analysis
Time
I(L
1
)
0A
1.0A
2.0A
3.0A
V(OUT)
0V
10V
20V
25V
SEL>>
Averaged-inductor model for a
voltage-mode boost converter
C
1
100u
IC = 0
V
1
10
R
2
20
R
1
10m
0.5
out
U7 BOOSTVM
Rs = 1
FS = 1k
L = 10m
DON
IN OUT
GND
R
3
1
0
+
-
Output voltage obtained with the
averaged-inductor model
Time
V(OUT)
0V
5V
10V
15V
20V
25V
30V
Measuring the loop gain
Measuring the loop gain
Frequency
1.0mHz 10mHz 100mHz 1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz
P(V(VF))
-360
-270
-180
-90
0
90
SEL>>
(100.000,-163.029)
DB(V(VF))
-80
-40
0
20
(100.000,-1.2488)
Frequency compensation
choose f1 = 100 Hz for a switching frequency of 1 kHz
PID compensation
1 1 1 1
1
( ) 90 2tan 2tan
comp
z p
f f
f
f f

_
_
+

,
,
2
2
1 1
1 10 1 10 10
( ) 20 (2 ) 40 1 40 1
comp
z p
f f
M f Log f Log Log
f f
_
_
_
_

+ + +

,
,
,
,
1
1
1
1
90 2tan
tan
2
comp
p
z
z
f
f
f
f
f

_
_
+ +

,

,
( )
2
2 1
1 10 1 10 1 10
( ) 20 (2 ) 40 1 40 1
comp z
p
f
M f Log f Log f Log
f
_
_

+ + +

,
,
PID compensation
1 p
3 3
1
= f
2
C R
2
1 2
p
2 1 2
( + )
C C
= f
2
C C R
1 z
2 1
1
= f
2
C R
2 z
1 3 3
1
= f
2 ( + )
C R R
2
1
1
R
=
K
R
2 1 3
2
1 3
( + )
R R R
=
K
R R
3 1 2
3
2 1 2
C C R
= .
C
+
C C R
Mag_comp_f1 = -7.0985
Ph_comp = 32
k1_db = -24.6094
k1 = 0.0588
k2_db = -5.0259
k2 = 0.5607
R2 = 588.2076
R3 = 269.7258
C1 = 5.0034e-005
C2 = 1.3496e-006
C3 = 2.8658e-006
Boost switching converter with
PID compensator
-15
pwm
R
s
1
+15
saw
C
out
100uF
IC = 20
L
1
10mH
IC = 4
C
1
5.0014e-005
R
2
518.3291
V
1
10V
dc
0
R
1
10k
0
-15
sense
R
6
100
V
3
-15
out
5
+15
LM311
+
- G
V
+
V
-
B/S
B
R
s3
1k
0
0
D
1
MUR420
+15
C
3
2.5483e-006
Error amplifier
R
20
R
4
10meg
V
ref
V
4
TD = 0
TF = 1n
PW = 1n
PER = 1m
V1 = 0
TR = 999u
V2 = 10
R
s2
3k
TL084
+
-
V
+
V
-
E
SR
10m
R
8
300
R
3
173.0498
V
2
`15
control
V
X2
MTP15N05E/MC
PWM
modulator
C
2
1.1461e-006
-15
pwm_out
+
-
Simulation results with a PID
compensator
Time
V(out)
0V
20V
40V
V(control)
5.0V
7.5V
10.0V
SEL>>
I(L
1
)
4.0A
4.5A
5.0A
PI compensation
0
C
out
200uF
IC = 0
0
EAO
0
10
-10
L
1
10mH
IC = 0
V
g
10V
dc
R
s
1
out
100k
R
esr
10m
0
10
10 + s
error
R
20
V
f
0
R
1
1k
V
1
1V
ac
0V
dc
V
f
C
1
500n
U7
VMSSCCM
D = 0.5
IC = -1.84
RD = 1e-6
RE = 10m
RM = 1e-6
RMPHITE = 10
RSW = 10m
VAP = -17.6
1
3
2
4
A
C
P
V
C
0
-
+
+
-
E1
E
GAIN = 0.25
R
2
10k
+
-
Small-signal model of the boost converter with PI
compensation
1 1
1 2
1 s C R
TF
s C R
+

PI compensation
Frequency
1.0mHz 10mHz 100mHz 1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz
P(V(VF)) P(V(EAO))
-360
-270
-180
-90
0
90
180
DB(V(VF)) DB(V(EAO))
-200
-100
0
SEL>>
Compensated loop gain
Uncompensated loop gain
Compensated loop gain
Uncompensated loop gain
100
PI compensation using ABM
blocks
0
saw
R
esr
10m
0
5
1
1 + s
out
D
break
D
1
10
-10
R
2
10k
R
1
1k
R
3
100k
if( V(%IN1) < V(%IN2),1,0)
1
3
2
V
2 TD = 0
TF = 0.05u
PW = 0.05u
PER = 100u
V1 = 0
TR = 99.9u
V2 = 10
C
1
500n
C
2
1n
+
-
+
-
S
1
S
VON = 1.0V
VOFF = 0.0V
C
out
100u
IC = 20
R
s
0.1
ref
0
0
R
20 gate
100k
L
1
10mH
IC = 1.8
1 2
V
1
10V
dc
pwm
control
0.25
+
-
Simulation results of the PI
compensation using ABM blocks
Time
V(CONTROL)
0V
5V
10V
V(OUT)
0V
10V
20V
30V
SEL>>
I(L
1
)
0A
2.0A
4.0A
PI compensation using vendor
models
R
3
10
0
R
1
1k
-15
+15
V
1
10V
dc
V
2
TD = 0
TF = 0.05u
PW = 0.05u
PER = 100u
V1 = 0
TR = 99.9u
V2 = 10
-15
C
out
100u
IC = 20
0
ref
0
0
gate
out
X
1
MTP15N05E/MC
R
20
0
R
s
0.1
V
3
+15V
dc
C
1
500n
LM311
+
-
G
V
+
V
-
B/S
B
R
6
1k
TL084
+
-
V
+
V
-
5
0
L
1
10mH
IC = 1.8
1 2
R
5
3k
0
R
2
10k
saw
-15
R
esr
10m
control
+15
pwm
V
4
-15V
dc
D
2
MUR420
R
4
300
+15
+
-
Simulation results of the PI
compensation using vendor
models
Time
V(CONTROL)
0V
5V
10V
SEL>>
V(OUT)
0V
20V
40V
I(L
1
)
0A
2.0A
4.0A
PI compensation using vendor
models
*Analysis directives:
.TRAN 0 30m 0 10n SKIPBP
.OPTIONS STEPGMIN
.OPTIONS PREORDER
.OPTIONS ABSTOL= 10.0p
.OPTIONS CHGTOL= 0.1p
.OPTIONS ITL2= 200
.OPTIONS ITL4= 400
.OPTIONS RELTOL= 0.01
.OPTIONS VNTOL= 10.0u
I/O ERROR -- Probe file size exceeds 2000000000
JOB ABORTED
TOTAL JOB TIME 912.11
Creating capture symbols for PSpice
simulation
Vendors often provide PSpice models for their circuit

components. They are normally provided in a text file with
extension .LIB; if the file has a different extension, it should
be changed to .LIB
Start the PSpice Model Editor and from the File menu, choose
Create Parts
Browse to find the input model library (.LIB file) and click
OK to start
This step creates an .OBL file with a schematic symbol linked

to your model
To place the new part into the schematic, open Capture, and
from the Place menu choose Part. Click Add library, then find
and add the new .OLB file
Solving convergence problems
PSpice uses the Newton-Raphson algorithm to

solve the nonlinear equations in these analyses

The algorithm is guaranteed to converge only if the

analysis is started close to the solution
If the initial guess is far away from the solution, this

may cause a convergence failure or even a false
convergence
If the node voltages do not settle down within a

certain number of iterations, an error message will
be issued
DC analysis error messages
The DC Analysis calculates the small-signal bias

points before starting the AC analysis or the initial
transient solution for the transient analysis
Solutions to the DC analysis may fail to converge

because of incorrect initial voltage guesses, model
discontinuities, unstable or bistable operation, or
unrealistic circuit impedances
When an error is found during the DC analysis,

SPICE will then terminate the run because both the
AC and transient analyses require an initial stable
operating point in order to start
DC analysis error messages
No convergence in DC analysis
PIVTOL Error
Singular Matrix
Gmin/Source Stepping Failed
No Convergence in DC analysis at Step = xxx

Transient analysis error messages
If the node voltages do not settle down, the time

step is reduced and SPICE tries again to determine
the node voltages
If the time step is reduced beyond a certain fraction

of the total analysis time, the transient analysis will
issue an error message Time step too small and
the analysis will be halted
Transient analysis failures are usually due to model

discontinuities or unrealistic circuit, source, or
parasitic modeling
Solutions to convergence
problems
There are two ways to solve convergence problems
the first only tries to fix the symptoms by adjusting the

simulator options
while the other attacks the root cause of the

convergence problems
Once the circuit is properly modeled, many of the

modifications of the "options" parameters will no longer
be required
It should be noted that solutions involving simulation

options may simply mask the underlying circuit
instabilities
Bias point (DC) convergence
Checking circuit topology and connectivity

Modeling of circuit components
PSpice options are checked to ensure that

they are properly defined
Checking circuit topology and
connectivity
Make sure that all of the circuit connections are valid

Check for incorrect node numbering or dangling

nodes

Verify component polarity

Check for syntax mistakes

Make sure that the correct PSpice units (i.e. MEG

for 1E6, not M, which means mili in simulations) are
used
Make sure that there is a DC path from every

node to ground
Make sure that there are at least two connections

at every node

Make sure that capacitors and/or current sources

are not connected in series
Make sure that no (groups of) nodes are isolated

from ground by current sources and/or capacitors
Make sure that there are no loops of inductors

and/or voltage sources only
Place the ground (node 0) somewhere in the

circuit
Be careful when floating grounds (e.g., chassis

ground) are used; a large resistor should be
connected from the floating node to ground. All
nodes will be reported as floating if "0 ground" is
not used
Make sure that voltage/current generators use

realistic values, and verify that the syntax is
correct
Make sure that dependent source gains are

correct, and that E/G element expressions are
reasonable
Verify that division by zero or LOG(0) cannot

occur
Voltages and currents in PSpice are limited to the

range +/- 1e10
Avoid using digital components, unless really

necessary
Initialize the digital nodes with valid digital values

Avoid situations where an ideal current source

delivers current into a reverse-biased p-n junction
without a shunt resistance
Setting up the options for the
analog simulation
Increase ITL1 to 400
Use NODESETs to set node voltages to the nearest

reasonable guess at their DC values
Enable the GMIN stepping algorithm
Set PREORDER in Simulation Profiles options
Setting the value of ABSTOL to 1
PSpice does not always converge when relaxed

tolerances are used
Setting GMIN to a value between 1n and 10n will often

solve convergence problems
Setting GMIN to a value, which is greater than 10n,

may cause convergence problems
Transient convergence
The transient analysis can fail to complete if

the time step becomes too small
This can be due to either
(a) the Newton-Raphson iterations would not

converge even for the smallest time step size
(b) something in the circuit is moving faster than

can be accommodated by the minimum step size
Transient convergence
The circuit topology and connectivity should

first be checked
Followed by the PSpice options

Circuit topology and
connectivity
Avoid using digital components, unless really

necessary
Initialize the nodes with valid digital value to ensure

there are no ambiguous states
Use RC snubbers around diodes
Add Capacitance for all semiconductor junctions

connectivity
Add realistic circuit and element parasitics
It is important that switching times be

nonzero
It is recommended that all inductors have a

parallel resistor

Look for waveforms that transition vertically

(up or down) at the point during which the
analysis halts
connectivity
Increase the rise/fall times of the PULSE

sources
Ensure that there is no unreasonably large

capacitor or inductor
PSpice options
Set RELTOL=.01
Reduce the accuracy of ABSTOL/VNTOL if

current/voltage levels allow it
ABSTOL and VNTOL should be set to about 8

orders of magnitude below the level of the maximum
voltage and current
Increase ITL4, but no more than 100

PSpice options
Skipping the bias point is not recommended
Any applicable .IC and IC= initial conditions

statements should be added to assist in the
initial stages of the transient analysis
Switching converter simulation using
Matlab
Working with transfer functions
Consider a buck converter designed to operate in the continuous conduction
mode having the following parameters: R = 4, L = 1.330 mH, C = 94 f, Vs =
42 V, Va = 12 V
$
1 2
2
2
0 0
1 1
( )
( )
1
o
z z
d
s s
s s
v s
K
s s
d s
Q
_ _
+

, ,
+ +
$
2
(1 )
s
d
V
K
D
1
1
z
ESR
s
R C
2
2
(1 )
( || )
ind
z ESR
R D
s R R R
L L

0
(1 ) 1
ind e
ESR
R r D D
R R
LC
+
||
e ESR
r R R
0
(1 ) 1
( )
ind e
ESR
Q
R r D
L C R R
+
+
+
Matlab
% this is a comment
% parameters
R= 4;
L = 1.330 e-3;
Rind = 100 e-3;
C = 94 e-6;
Resr = 10 e-3
Vs = 42;
Va = 12;
D=Va/Vs;
Kd= Vs/(1-D)^2;
Sz1=1/(Resr*C);
Req = R-(Resr*R/(Resr+R));
Sz2 = (1/L)*(1-D)^2* Req Rind/L;
Re=(Resr*R)/( Resr+R);
Wo = (1/sqrt(L*C)) * sqrt((Rind+re*D*(1-D))/(Resr+R));
Q = Wo/(((Rind+re*(1-D))/L)+(1/(C*(Resr+R))));
Matlab
% polynomials are entered in descending order of S.
n1=[1/Sz1 1]
n2=[-1/Sz2 1]
NUM=conv(n1,n2)
% the convolution realizes the product of 2 polynomials
% define denumerator
DEN = [1/(Wo^2) 1/(Wo*Q) 1]
% create TF variable
sysTF = Kd * tf(NUM,DEN)
which returns
Transfer function:
-5.317e-008 s^2 - 0.05648 s + 82.32
4.913e-006 s^2 + 0.01343 s + 1
sysTF
Matlab
The location of the poles can be
found using
poles = roots(DEN)
and the frequency response can be
plotted using
bode(sysTF)
Bode Diagram
Frequency (rad/sec)
P
h
a
s
e
(
d
e
g
)
M
a
g
n
i
t
u
d
e
(
d
B
)
-40
-20
0
20
40
10
1
10
2
10
3
10
4
10
5
10
6
10
7
-270
-225
-180
-135
-90
-45
0
Matlab
The small signal transient step response can be plotted using
Figure % this command opens a new figure window
step(sysTF) Step Response
Time (sec)
A
m
p
l
i
t
u
d
e
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
-10
0
10
20
30
40
50
60
70
80
90
Matlab
Working with matrices
Consider a buck converter designed to operate in the continuous conduction mode
having the following parameters: R = 4, L = 1.330 mH, C = 94 f, Vs = 42 V,
Va = 12 V.
% state-space averaged model of a Buck converter
Rload= 4;% load resistance
L= 1.330e-3; % inductance
cap=94.e-6; % capacitance
Ts=1.e-4; % switching period
Vs=42; % input DC voltage
Vref=12; % desired output voltage
The average duty cycle is:
D=Vref/(Vs); % ideal duty cycle
Matlab
^
^ ^ ^
1
^
2
1
0
1 1
0 0
s
V D
x
L
x u d
L L
x
C RC
1 1 1 1
1 1 1 1
+ +
1 1 1 1
] ] ] ]
A=[ 0 -1/L
1/cap -1/(Rload*cap)]
B1=[ 1/L
0]; %during Ton

B2=[ 0
0]; %during Toff
B=B1*D+B2*(1-D)

C=[0 1];
Matlab
OLpoles = eig(A)
sysOL=ss(A,B,C,0)
step(sysOL)
Time (sec.)
A
m
p
l
i
t
u
d
e
Step Response
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
x 10
-3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
From: U (1)
T
o
:
Y
(
1
)
Matlab
gamma=[ Vs/L
0];
closed-loop poles:
P=1e3*[-0.3298 + 0.10i -0.3298 - 0.10i]';
Bf= gamma*(D/Vref);
F=place(A,Bf ,P)
Simulink
-5.317e-8 s^2 - 0.05648 s + 82.32
4.913e-6 s^2 + 0.01343 s + 1
sysTF
[NUM,DEN] = TFDATA(sysTF,v)
-5.317e-8s -0.0565s+82.32
2
4.913e-6s +0.0134s+1.0
2
Transfer Fcn
time
To Workspace1
output
To Workspace
Step Scope
Clock
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05
-10
0
10
20
30
40
50
60
70
80
90
Time (s)
O
u
t
p
u
t
Simulink
sysZPK = zpk(sysTF)
-0.010821 (s+1.064e006) (s-1455)
(s+2657) (s+76.6)
sysZPK
zeroes: [-1.0638e+006 +1455]
poles: [-2657 -76.6]
gain: [-0.010821]
Simulink
[ ]
[ ]
0 752
10638 2660
214.82 0 '
0 1 '
0
A
B
C
D
1
time
To Workspace1
output
To Workspace
Step
x' = Ax+Bu
y = Cx+Du
State-Space
Scope
Clock

Simulation of Switching Converters

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Simulation of Switching Converters

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Time

PSpice Simulations using .CIR

PSpice Simulations using schematics entry

PSpice Simulations Using Behavioral Modeling

PSpice simulations using vendor models

Small-signal analysis of switching converters

Creating capture symbols for PSpice simulation

Solving convergence problems

ABM.OLB part library

Control system parts

Power switching converters Simulation of switching converters 67

Vendors often provide PSpice models for their circuit

This step creates an .OBL file with a schematic symbol linked

PSpice uses the Newton-Raphson algorithm to

The algorithm is guaranteed to converge only if the

If the initial guess is far away from the solution, this

If the node voltages do not settle down within a

The DC Analysis calculates the small-signal bias

Solutions to the DC analysis may fail to converge

When an error is found during the DC analysis,

Gmin/Source Stepping Failed

No Convergence in DC analysis at Step = xxx

If the node voltages do not settle down, the time

If the time step is reduced beyond a certain fraction

Transient analysis failures are usually due to model

There are two ways to solve convergence problems

the first only tries to fix the symptoms by adjusting the

while the other attacks the root cause of the

Once the circuit is properly modeled, many of the

It should be noted that solutions involving simulation

Checking circuit topology and connectivity

Modeling of circuit components

PSpice options are checked to ensure that

Make sure that all of the circuit connections are valid

Check for incorrect node numbering or dangling

Verify component polarity

Check for syntax mistakes

Make sure that the correct PSpice units (i.e. MEG

Make sure that there is a DC path from every

Make sure that there are at least two connections

Make sure that capacitors and/or current sources

Make sure that no (groups of) nodes are isolated

Make sure that there are no loops of inductors

Place the ground (node 0) somewhere in the

Be careful when floating grounds (e.g., chassis

Make sure that voltage/current generators use

Make sure that dependent source gains are

Verify that division by zero or LOG(0) cannot

Voltages and currents in PSpice are limited to the

Avoid using digital components, unless really

Initialize the digital nodes with valid digital values

Avoid situations where an ideal current source

Increase ITL1 to 400

Use NODESETs to set node voltages to the nearest

Enable the GMIN stepping algorithm

Set PREORDER in Simulation Profiles options

Setting the value of ABSTOL to 1

PSpice does not always converge when relaxed

Setting GMIN to a value between 1n and 10n will often

Setting GMIN to a value, which is greater than 10n,

The transient analysis can fail to complete if

This can be due to either

(a) the Newton-Raphson iterations would not

(b) something in the circuit is moving faster than