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Introduction Block Diagram and Pin Description of the 8051 Registers Memory mapping in 8051 Stack in the 8051 Interrupts Applications
there is no electronic gadget on the earth which is designed without a Microcontroller. Ex: communication devices, digital entertainment, portable devices etc
pager, watch, pocket recorder, calculator Laptop components: mouse, keyboard, modem, fax card, sound card, battery charger Home appliances: door lock, alarm clock, thermostat, air conditioner, TV remote, VCR, small refrigerator, exercise equipment, washer/dryer, microwave oven Industrial equipment: Temperature/pressure controllers, Counters, timers, RPM Controllers Toys: video games, cars, dolls, etc.
Microcontroller Applications
CP U
RAM
CPU for Computers No RAM, ROM, I/O on CPU chip itself Example Intels x86, Motorolas 680x0 CPU GeneralPurpose Microprocesso r Data Bus RAM ROM I/O Port Time r Seri al COM Port
Address Bus
(ROM)
Operation of stack
push pop
memory and generally connects to an EPROM The PSEN signals goes LOW during an instruction fetch and remains HIGH during execution of an instruction.
ALE
Address Latch Enable is used by 8051 for de-multiplexing the
EA(External Access)
If the EA pins goes HIGH, the 8051 execute program from internal
RST(Reset)
It is used to reset 8051 microcontrollers
Power Connection
8051 requires a single +5V power supply for its operations
Internal Memory
There are 128 bytes of RAM in the 8051 Assigned addresses 00 to 7FH The 128 bytes are divided into three different groups as follows: A total of 32 bytes from locations 00 to 1F hex are set aside for register banks and the stack.
Bits RS0 and RS1 in the PSW determine which bank of register is currently Is use. Bank 0 is selected upon reset.
A total of 16 bytes from locations 20H to 2FH are set aside for bit-addressable read/write memory. A total of 80 bytes from locations 30H to 7FH are used for read and write storage. Four register banks: 00 to 1F hexadecimal.
External memory
External memory is used in cases when the internal ROM and RAM memory Available On chip is not sufficient. Two separate are made available by the 16-bit PC and the DPTR and by different control pins for enabling external ROM and RAM chips. If the 128 bytes of internal RAM is insufficient, the external RAM is accessed by the DPTR. In the 8051 family, external RAM of upto 64 KB can be added to any chip.
Timer/Counters
Two 16-bit up counters, named T0 and T1, are provided for the general use of the programmer. The 8051 has two timers/counters, they can be used either as Timers to generate a time delay or as Event counters to count events happening outside the microcontroller Both Timer 0 and Timer 1 are 16 bits wide Since 8051 has an 8-bit architecture, each 16-bits timer is accessed as two separate registers of low byte and high byte The counters are divided into two 8-bit registers called the timer low (TL0,TL1) and high (TH0, TH1) bytes.
8051 Interrupts
An interrupt is the occurrence of a condition an
asynchronous events (not in program flow) and handle the events while another task is running. called an Interrupt Service Routine (ISR) or an interrupt handler of either an external or an internal event.
Interrupt Service
particular interrupt occurs? 8051 Interrupt Vector Table (Atmel 89C51RD2 has 3 more not covered) Interrup Vector Number Pin Flag Comment
t Reset INT0 TF0 INT1 TF1 RI/TI TF2/EXF 2 Address 0000H 0003H 000BH 0013H 001BH 0023H 002Bh Bytes 3 8 8 8 8 8 3 P3.3 P3.2 Clearing Auto Auto Auto Auto Auto Programmer Programmer Power-on External Hardware Timer 0 External Hardware Timer 1 Serial Communication Timer 2
current PC Stack Vectors (i.e. jumps) to the corresponding location within the interrupt vector table, i.e. PC Vector Table address Option 1: If the ISR fits in the available space you can immediately service the interrupt Option 2: If the ISR is too large then the vector table contains a long jump (ljmp) to the Interrupt Service Routing (ISR) The last instruction of the ISR is a reti (Return from Interrupt) Responsibility of ISR to save/restore any registers that it uses, including the PSW, having the same number of pushes and pops to/from the stack for the reti instruction
Each interrupt type has a separate vector address. Each interrupt type can be programmed to one of two priority levels.