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Hence, reducing power consumption has become a major challenge in the design and operation of todays Portable and Handheld Embedded devices
In 1965, Intels Gordon Moore predicted that the number of transistors that can be integrated on single chip would double about every two years
feature size & die size
Moores Law
Dual Core Itanium with 1.7B transistors
Classification Of DPM
Reduce the physical capacitance or stored electrical charge of a circuit. Lower dynamic power is to reduce the switching activity. Reduce dynamic power consumption is to reduce the clock frequency. Reduce dynamic power consumption is to reduce the supply voltage
Low-Power Interconnect
Bus Encoding And CrossTalk. Low Swing Buses. Bus Segmentation. Network-On-Chip
Architectural Overview
POLICY MANAGER USER/ APPLICATION SPACE
POLICIES
OS KERNEL DPM
Resource Hibernation
Disk Drives. Network Interfaces. Displays.
Cross-Layer Adaptations
This approaches gives the very effective power management . It adopt OS Level, Compiler level as well as middleware level approach to solve the power need of the entire system
Research Labs
IBM Research Lab USC Information Sciences Institute Computer Architecture and Power Aware Systems Research Group , BINGHAMTON UNIVERSITY Lattice Semiconductor Transmeta Research Lab Intel Research Lab