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Power aware embedded systems

R.Prabakaran Center for Convergence of Technologies Anna University Tiruchirappalli

Need for Power Management


Current scenario
Mobile Phone Laptop MP3 Players MPEG 4 Players 1 to 3 Hrs active time 1.30 to 2 Hrs active time 8 to 12 Hrs 3-6 Hrs

Hence, reducing power consumption has become a major challenge in the design and operation of todays Portable and Handheld Embedded devices

In 1965, Intels Gordon Moore predicted that the number of transistors that can be integrated on single chip would double about every two years
feature size & die size

Moores Law
Dual Core Itanium with 1.7B transistors

Intel 4004 Microprocessor


1971 0.2 MHz clock 3 mm2 die 10,000 nm feature size ~2,300 transistors 2mW power

Intel Pentium (IV) Microprocessor


2001 30 (15*2) years 1.7 GHz clock 8500x faster 271 mm2 die 90x bigger die 180 nm feature size 55x smaller feature size ~42M transistors 18,000x more Ts 64W power 32,000x (215) more power

Power and Energy


Power is the rate at which the systems does the work
P = W/T

Energy is the amount of work a systems perform over a period of time


E=PT

Static Vs Dynamic Power Consumption


Static Power mode the processor consume the same amount of power for all applications In Dynamic Power consumption the processor will consume power based on its application

Dynamic Power Consumption


Pdynamic ~ ~ aCV2 f .
V- supply voltage f- frequency C- physical capacitance a-Activity factor(0 1 or 1 0)

Cause for Dynamic Power Consumption


Switched capacitance Short-circuit current

Classification Of DPM
Reduce the physical capacitance or stored electrical charge of a circuit. Lower dynamic power is to reduce the switching activity. Reduce dynamic power consumption is to reduce the clock frequency. Reduce dynamic power consumption is to reduce the supply voltage

Understanding Leakage Power Consumption


In addition to consuming dynamic power, computing components consume static power, also known as idle power or leakage.
Pleak = V Ileak

Leakage current in transistor


Reverse-biased-junction leakage Gate-induced-drain leakage Sub threshold leakage Gate-oxide leakage Gate-current leakage and Punch-through leakage.

Various Ways to Reduce the Power


Circuit And Logic Level Techniques Low-Power Interconnect Low-Power Memories and Memory Hierarchies Low-Power Processor Architecture Adaptations Dynamic Voltage Scaling Resource Hibernation Compiler-Level Power Management Application-Level Power Management Cross-Layer Adaptations

Circuit And Logic Level Techniques


Transistor Sizing. Transistor Reordering. Half Frequency and Half Swing Clocks. Logic Gate Restructuring. Technology Mapping Low Power Flip Flops Delay-Based Dynamic-Supply Voltage Adjustment

Low-Power Interconnect
Bus Encoding And CrossTalk. Low Swing Buses. Bus Segmentation. Network-On-Chip

Low-Power Memories and Memory Hierarchies


Splitting Memories Into Smaller Subsystems. Augmenting the Memory Hierarchy With Specialized Cache Structures.

Low-Power Processor Architecture Adaptations


Adaptive Caches. Adaptive Instruction Queues.

Dynamic Voltage Scaling


Unpredictable Nature Of Workloads. Indeterminism And Anomalies In Real Systems. Interval-Based Approaches. Intertask Approaches. Intratask Approaches The Implications of Memory Bounded Code.

Dynamic Voltage Frequency Scaling


The combination of scaling the supply voltage and clock frequency in tandem is called dynamic voltage scaling (DVS).

Architectural Overview
POLICY MANAGER USER/ APPLICATION SPACE

POLICIES

OS KERNEL DPM

Resource Hibernation
Disk Drives. Network Interfaces. Displays.

Compiler-Level Power Management


Remote Compilation and Remote Execution The Limitations of Statically Optimizing Compilers. Dynamic Compilation.

Application-Level Power Management


Application Transformations and Adaptations Application Hints.

Cross-Layer Adaptations
This approaches gives the very effective power management . It adopt OS Level, Compiler level as well as middleware level approach to solve the power need of the entire system

The Commercial Support


The Pentium M Processor. The Intel PXA27x Processors. The Transmeta Crusoe Processor. IBM Dynamic Power Management. Powerwise and Intelligent Energy Management (ARM)

Research Labs
IBM Research Lab USC Information Sciences Institute Computer Architecture and Power Aware Systems Research Group , BINGHAMTON UNIVERSITY Lattice Semiconductor Transmeta Research Lab Intel Research Lab

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