I2C PROTOCOL

By -Gauri

WHAT IS I2C ?

Inter-IC (I2C) is a simple bi-directional 2-wire serial bus protocol for inter IC control. Introduced by Philips Semiconductors in 1980s. Its purpose: to provide a communication link between Integrated Circuits.

NEED OF I2C

Connecting peripheral devices to the c requires the c's parallel address and data bus. Increases wiring on the PCB, address decoders and needs glue logic. Hence, system is more susceptible to EMI and Electrostatic Discharge (ESD). These problems are overcome by I2C.

I2C BUS TERMINOLOGY

Transmitter- device that sends data to bus Receiver- receives data from bus Master- initiates data transfer, generates clock, terminates data transfer Slave- device addressed by a master

Multi-master more than 1 master in system

FEATURES OF I2C

1. 2.

Only 2 bus lines required-Serial Clock Line (SCL), Serial Data Line (SDA). Each device has unique address. Simple master-slave relationship. A true multi-master buscollision detection Arbitration On-chip filtering rejects spikes.

FEATURES OF I2C

Maximum no. of ICs that can be connected to the same bus is limited only by a maximum bus capacitance of 400pF.

1. 2. 3.

Serial,8-bit oriented, bi-directional data transfer at up to 100 kbps in Standard mode 400 kbps in Fast mode 3.4 Mbps in High speed mode.

I2C BUS HARDWARE

2 active wires- serial clock line (SCL), serial data line (SDA) and a ground. These signals use open collector or open drain o/ps (depending on the technology).
When the bus is IDLE, the bus lines are in the logic HIGH state. To put a signal on the bus, the chip drives its o/p transistor, thus pulling the bus to a LOW level.

I2C BUS CONFIGURATION

Master-transmitter Master-receiver

I2C SIGNALS

Start condition Repeated start

Stop condition Acknowledge Data transfer

DATA TRANSFER

TRANSMITTING AND RECEIVING A BYTE

ACKNOWLEDGE

Getting acknowledge from a slave devicemaster transmitter configuration

Giving acknowledge to a slave device-master receiver configuration

N-ACKNOWLEDGE

An Acknowledge of a byte received from a slave is always necessary, EXCEPT on the last byte received.

Condition

Can only occur...

Not acknowle dge (NACK)

after a master has read a byte from a slave

No acknowle dge

after a master has written a byte to a slave

ADDRESSING

Address formats- 7-bit address format(outdated),10-bit address format I2C standard has been updated to implement a 10-bit addressing mode. Fig. shows 7-bit addressing format.

ARBITRATION

Procedure that ensures only 1 master will control the bus in multi-master system. Hence, data transfer does not get corrupted.

ARBITRATION

The moment the data bits of the 2 CPUs do not match anymore CPU2 loses arbitration (shown in yellow) and backs off.CPU2 does not get its data on the bus.

MODES OF I2C
EXTENTIONS TO THE STANDARD-MODE(100 kbps)

ENHANCED/FAST MODE (400 kbps)

HIGH-SPEED/Hs-MODE (3.4 Mbps)

EXTENDED ADDRESSING 10-bit

ENHANCED I2C/FAST MODE (400 kbps)

Physical bus parameters, protocol, bus levels, capacitive load-remain unchanged. Constraint on the level of noise that can be present in the system. CBUS devices cannot handle the higher clock rates, hence all CBUS activities are cancelled.

ENHANCED I2C/FAST MODE

I/ps include Schmitt triggers to suppress noise. O/p buffers include slope control for the falling edges of the SDA and SCL signals. If power supply is switched off, bus pins must be floating so that they do not obstruct the bus. The pull-up resistor must be adapted to accommodate the shorter maximum permissible rise time.

HIGH-SPEED/Hs-MODE (3.4 Mbps)

Arbitration and clock synchronization is not performed during the Hs-mode transfer. A serial clock signal with a HIGH to LOW ratio of 1 to 2 - relieves the timing requirements for set-up and hold times. SDAH and SCLH lines are separated by builtin bridge from the SDA and SCL linesreduces the capacitive load of the SDAH and SCLH lines

HIGH-SPEED/Hs-MODE

I/ps incorporate spike suppression and a Schmitt trigger at the SDAH and SCLH i/ps. O/p buffers incorporate slope control of the falling edges of the SDAH and SCLH signals. Devices have an open-drain o/p buffer for the SDAH signal and a combination of an opendrain pull-down and current-source pull-up circuit on the SCLH o/p.

EXTENDED ADDRESSING 10-bit

1.

2.

Need for extended addressing- 7-bit address space got exhausted. Slave receives two address bytesextended addressing reserved address including the 2 MSB's of the device address and the Read/Write bit 8 LSB's of the address.

ADVANTAGES

Easy to link multiple devices because of addressing scheme. Cost and complexity do not scale up with the number of devices. Good for communication with on-board devices.

DISADVANTAGES

Long lines present a capacitive load for the output drivers. It can lead to faulty reception of data.

The assignment of slave addresses is one weakness of IC(7-bit addressing). I2C's lower speed and more complex protocol put it at a disadvantage in single master-single slave applications.

APPLICATIONS

Accessing NVRAM chips that keep user settings. Accessing low speed DACs, ADCs. Changing contrast, hue, and color balance settings in monitors (Display Data Channel). Controlling LED/LCD displays, like in a cellphone. Reading real time clocks.

COMPARISON WITH SM BUS

Both the SMBus and the I2C bus are two wire open collector buses with a high level of compatibility. Mixing SMBus and I2C bus master and slave devices often works without any problems if no I2C master uses a clock speed above 100 kbps. Summary of Significant Differences Timeout and minimum clock speed(DC,10kHz) Voltage levels Pullup resistor values and current levels

COMPARISON

I2C Lower speed, half duplex and more complex protocol Disadvantageous in single master-single slave applications Advantageous for multiple slave or multimaster system

SPI and Microwire Full duplex capability and fast data rates Makes the interfaces very efficient Simple for single master - single slave applications

THANK YOU !!!