Jaeger/Blalock

9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 1
Chapter 6
Introduction to Digital Electronics
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 2
Chapter Goals
Introduce binary digital logic concepts
Explore the voltage transfer characteristics of ideal and
nonideal inverters
Define logic levels and logic states of logic gates
Introduce the concept of noise margin
Present measures of dynamic performance of logic devices
Review of Boolean algebra
Investigate simple transistor, diode, and diode-transistor
implementations of the inverter and other logic circuits
Explore basic design techniques of logic circuits

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 3
Brief History of Digital Electronics
Digital electronics can be found in many applications in
the form of microprocessors, microcontrollers, PCs, DSPs,
and an uncountable number of other systems.
The design of digital circuits has progressed from resistor-
transistor logic (RTL) and diode-transistor logic (DTL) to
transistor-transistor logic (TTL) and emitter-coupled logic
(ECL) to complementary MOS (CMOS)
The density and number of transistors in microprocessors
has increased from 2300 in the 1971 4-bit 4004
microprocessor to 25 million in the more recent IA-64 chip
and it is projected to reach over one billion transistors by
2010
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 4
Ideal Logic Gates
Binary logic gates are the most common style of
digital logic

The output will consist of either a 0 (low) or a 1 (high)

The most basic digital building block is the inverter


Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 5
The Ideal Inverter
The ideal inverter has the following voltage transfer characteristic
(VTC) and is described by the following symbol

V
+
and V
-
are the supply rails, and V
H
and V
L
describe
the high and low logic levels at the output
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 6
Logic Level Definitions
An inverter operating with power supplies at V
+
and
0 V can be implemented using a switch with a
resistive load
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 7
Logic Voltage Level Definitions
V
L
The nominal voltage corresponding to a low-logic
state at the input of a logic gate for v
i
= V
H

V
H
The nominal voltage corresponding to a high-logic
state at the output of a logic gate for v
i
= V
L

V
IL
The maximum input voltage that will be recognized
as a low input logic level
V
IH
The maximum input voltage that will be recognized
as a high input logic level
V
OH
The output voltage corresponding to an input
voltage of V
IL

V
OL
The output voltage corresponding to an input
voltage of V
IH


Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 8
Logic Voltage Level Definitions (cont.)
Note that for the VTC of the nonideal inverter, there is now an
undefined logic state
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 9
Noise Margins
Noise margins represent safety margins that
prevent the circuit from producing erroneous
outputs in the presence of noisy inputs
Noise margins are defined for low and high input
levels using the following equations:

NM
L
= V
IL
V
OL

NM
H
= V
OH
V
IH

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 10
Noise Margins (cont.)
Graphical representation of
where noise margins are
defined
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 11
Logic Gate Design Goals
An ideal logic gate is highly nonlinear that attempts to
quantize the input signal to two discrete states, but in an
actual gate, the designer should attempt to minimize the
undefined input region while maximizing noise margins
The input should produce a well-defined output, and
changes at the output should have no effect on the input
Voltage levels of the output of one gate should be
compatible with the input levels of a proceeding gate
The gate should have sufficient fan-out and fan-in
capabilities
The gate should consume minimal power (and area for
ICs) and still operate under the design specifications
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 12
Dynamic Response of Logic Gates
An important figure of merit to describe logic
gates is their response in the time domain
The rise and fall times, t
f
and t
r
, are measured at
the 10% and 90% points on the transitions
between the two states as shown by the following
expressions:
V
10%
= V
L
+ 0.1V

V
90%
= V
L
+ 0.9V = V
H
0.1V

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 13
Propagation Delay
Propagation delay describes the amount of time between a
change at the 50% point input to cause a change at the 50%
point of the output described by the following:



The high-to-low prop delay,
PHL
, and the low-to-high prop
delay,
PLH
, are usually not equal, but can be described as
an average value:


2
PLH PHL
P
t t
t
+
=
2
L H
50%
V V
V
+
=
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 14
Dynamic Response of Logic Gates
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 15
Power Delay Product
The power-delay product (PDP) is use as a metric
to describe the amount of energy required to
perform a basic logic operation and is given by the
following equation when P is the average power
dissipated be the logic gate:
P
t P PDP =
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 16
Review of Boolean Algebra
A Z
0 1
1 0
A B Z
0 0 0
0 1 1
1 0 1
1 1 1
A B Z
0 0 0
0 1 0
1 0 0
1 1 1
NOT
Truth Table
OR
Truth Table
AND
Truth Table
A B Z
0 0 1
0 1 0
1 0 0
1 1 0
A B Z
0 0 1
0 1 1
1 0 1
1 1 0
NOR
Truth Table
NAND
Truth Table
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 17
Logic Gate Symbols and Boolean
Expressions
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 18
Diode Logic
Diodes can with resistive loads to implement
simple logic gates
Diode OR gate Diode AND gate
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 19
Diode Transistor Logic
Since diode gates are limited to AND and OR
functions, the diodes can be combined with
transistors to complete the basic logic functions
such as the following NAND gate
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 20
NMOS Logic Design
MOS transistors (both PMOS and NMOS) can be
combined with resistive loads to create single
channel logic gates

The circuit designer is limited to altering circuit
topology and width-to-length, or W/L, ratio since
the other factors are dependent upon processing
parameters
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 21
NMOS Inverter with a Resistive Load
The resistor R is used
to pull the output
high
M
S
is the switching
transistor
The size of R and the
W/L ratio of M
S
are
the design factors that
need to be chosen
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 22
Load Line Visualization
The following
illustrates the
operation of the
NMOS output (v
DS
)
characteristics where
the following
equation describes
the load line
R i V v
D DD DS
=
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 23
NMOS with Resistive Load Design
Example
Design a NMOS resistive load inverter for
V
DD
= 3.3 V
P = 0.1 mW when V
L
= 0.2 V
K
n
= 60 A/V
2

V
TN
= 0.75 V

Find the value of the load resistor R and the W/L
ratio of the switching transistor M
S


Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 24
Example continued
First the value of the current through the resistor
must be determined by using the following:


The value of the resistor can now be found by the
following which assumes that the transistor is on
or the output is low:
A
V
mW
V
P
I
DD
DD
3 . 30
3 . 3
1 . 0
= = =
O =

= k
A
V V
I
V V
R
DD
L DD
102
3 . 30
2 . 0 3 . 3

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 25
Example Continued
For v
I
= V
L
= 0.2V, the transistors v
GS
will be less
than the threshold voltage, therefore it will be
operating in the triode region. Using the linear
equation for a MOSFET, the W/L ratio can be
found:

( )
1
1
1
03 . 1
2 . 0
2
2 . 0
75 . 0 3 . 3 10 60 3 . 30
2
6
'
~ =
|
.
|

\
|
|
.
|

\
|

|
.
|

\
|
=
|
.
|

\
|

|
.
|

\
|
=

S
S
L
L
TN H
S
n D
L
W
L
W
A
V
V
V V
L
W
K I

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 26
On-Resistance of M
S

The NMOS resistive load
inverter can be thought of
as a resistive divider
when the output is low,
described by the
following expression:
R R
R
V V
on
on
DD L
+
=
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 27
On-Resistance of M
S
(cont.)

|
.
|

\
|

|
.
|

\
|
= =
2
1
'
DS
TN GS n
D
DS
on
v
V v
L
W
K
i
v
R
When the NMOS resistive load inverters output is
low, the On-Resistance of the NMOS can be
calculated with the following expression:
Note that R
on
should be kept small compared to R to
ensure that V
L
remains low, and also that its value is
nonlinear which has a dependence on v
DS

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 28
Noise Margin Analysis
The following equations can be used to determine
the various parameters needed to determine the
noise margin of NMOS resistive load inverters
R K
V
V
R K
V
R K
V V
R K
V V
R K
V V
n
DD
OL
n
DD
n
TN IH
n
DD OH
n
TN IL
3
2
63 . 1
1
2
1
1
=
+ =
=
+ =
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 29
Load Resistor Problems
For completely
integrated circuits, R
must be implemented on
chip using the shown
structure
Using the given
equation, it can be seen
that resistors take up a
large area of silicon as
in an example 95k
resistor
( )( )
1
9500
001 . 0
10 1 95
4
=
O
O
= =
=

cm
cm k Rt
W
L
tW
L
R

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 30
Using Transistors in Place of a Resistor
NMOS load w/
a) gate connected
to the source
b) gate connected
to ground
c) gate connected
to V
DD

d) gate biased to
linear region
e) a depletion
mode NMOS
Note that a) and b)
are not useful

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 31
Static Design of the NMOS Saturated
Load Inverter
Schematic for a NMOS
saturated load inverter
Cross-section for a NMOS
saturated load inverter
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 32
NMOS Saturated Load Inverter Design
Strategy
Given V
DD
, V
L
, and the power level, find I
DD
from V
DD
and
power
Assume M
S
off, and find high output voltage level V
H
Use the value of V
H
for the gate voltage of M
S
and
calculate (W/L)
S
of the switching transistor based on the
design values of I
DD
and V
L
Find (W/L)
L
(load transistor) based on I
DD
and V
L
Check the operating region assumptions of M
S
and M
L
for
v
o
= V
L
Verify design with a SPICE simulations
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 33
NMOS Saturated Load Inverter Design
Example
Design an saturated load inverter given the
following specifications:

A I
V V
V V
DD
L
DD
30
2 . 0
3 . 3
=
=
=
V
V
V V V
V A K
F
TO TN
n
6 . 0 2
5 . 0
75 . 0
/ 25
2 '
=
=
= =
=
|

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 34
NMOS Saturated Load Inverter Design
Example
First find V
H

( ) | |
( ) | |
V V V
V V
V V V V V V
H
H H
F F H TO DD TNL DD H
01 . 4 , 11 . 2
6 . 0 6 . 0 5 . 0 75 . 0 3 . 3
2 2
=
+ + =
+ + = = | |
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 35
NMOS Saturated Load Inverter Design
Example
For v
o
= V
L
,M
S
is
off (triode
region) and M
L
is
in saturation, find
the W/L ratios of
the two
transistors

( )
( )
( )
( ) ( )
19 . 2
1
81 . 0 2 . 0 3 . 3 10 25 30
81 . 0 6 . 0 6 . 0 2 . 0 5 . 0 75 . 0
1
76 . 4
2 . 0
2
2 . 0
75 . 0 11 . 2 10 25 30
2
2
6
2
'
6
'
=
|
.
|

\
|

|
.
|

\
|
=
= + + =

|
.
|

\
|
=
=
|
.
|

\
|
|
.
|

\
|

|
.
|

\
|
=
|
.
|

\
|

|
.
|

\
|
=

L
L
TNL
TNL GSL
L
n DL
S
S
L
L
TN H
S
n DS
L
W
L
W
A
V V
V V
L
W
K I
L
W
L
W
A
V
V
V V
L
W
K I

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 36
NMOS Saturated Load Inverter Design
Noise Margin Analysis
The basic noise margin equations are still the same as for
previous inverters, but there are different expressions for the
components

( )
( )
OL R
TNL OL DD OL
TNS IH
L
S
R
F F OL TO TNL
R
TNL DD
OL
TNL DD H OH
TNS IL
V K
V V V V
V V
L W
L W
K
V V V
K
V V
V
V V V V
V V
2 2
) / (
) / (
2 2
3 1

+ + =
=
+ + =
+

=
= =
=
| |
The equations can be written as a
quadratic equation,but an iterative
process must be used to solve for V
OL

and V
TNL
1) Choose an initial V
OL

2) Calculate the corresponding V
TNL

3) Update V
OL

4) Repeat 2 and 3 until the system
converges
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 37
NMOS Inverter with a Linear Load
Device
This alternative inverter
has a load transistor
that is biased with V
GG
defined by the
following:


This causes the load
transistor to operate in
the linear region
TNL DD GG
V V V + =
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 38
NMOS Inverter with a Depletion-mode
Load
With the addition of a
depletion-mode NMOS
(V
TH
< 0V), it is possible
to configure an inverter
as shown
V
GSL
= 0 V for this
configuration meaning
that M
L
is always
operating in saturation
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 39
Design of a NMOS Inverter with a
Depletion-mode Load
To find (W/L)
L
given i
DL
:



To find (W/L)
S
where V
H
= V
DD
use the same
technique as used for the resistor load inverter:

( )
2
'
2
TNL
L
n
DL
V
L
W K
i
|
.
|

\
|
=
L
L
TN H
S
n D
V
V
V V
L
W
K I
|
.
|

\
|

|
.
|

\
|
=
2
'
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 40
Noise Margins of a NMOS Inverter with
a Depletion-mode Load
R
TNL
TNS IH
R
TNL
OL
L S R
R R
TNL
TNS IL
R
R
TNL DD OH
K
V
V V
K
V
V
L W L W K
K K
V
V V
K
K
V V V
3
2
3
) / /( ) / (
1
1
2
=

=
=
+
=
|
|
.
|

\
|
+
+ =
The first two equations
assume the M
S
is saturated
and M
L
is in triode
The last two equations
assume the M
S
and M
L
are
in triode
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 41
NMOS Inverter Summary
Resistive load inverter takes up too much area for and IC
design
The saturated load configuration is the simplest design, but
V
H
never reaches V
DD
and has a slow switching speed
The linear load inverter fixes the speed and logic level
issues, but it requires an additional power supply for the
load gate
The depletion-mode NMOS load requires the most
processing steps, but needs the smallest area to achieve the
highest speed, V
H
= V
DD
, and best combination of noise
margins

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 42
Typical Inverter Characteristic
Inverter w/
Resistor
Load
Saturated
Load
Inverter
Linear
Load
Inverter
Inverter w/
Depletion-
Mode Load
V
H
5.0 V 3.4 V 5.0 V 5.0 V
V
L
0.25 V 0.25 V 0.25 V 0.25 V
N
ML
0.34 V 0.32 V 0.02 V 0.69 V
N
MH
1.43 V 0.69 V 2.78 V 2.25 V
Area (m
2
) 9500 6.92 9.36 4.21
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 43
NOR Gates
Simplified switch model for
the NOR gate with A on
Two-input NOR gate
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 44
NAND Gates
Simplified switch model
for the NOR gate with A
and B on (right)
Two-input NAND gate
(left)
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 45
NAND Gate Device Size Selection
The NAND switching transistors can be sized based on the
depletion-mode load inverter
To keep the low voltage level to be comparable to the
inverter, the desired R
ON
of M
A
and M
B
must be 0.5R
ON
of
M
S,Inverter

This can be accomplished by approximately doubling the
(W/L)
A
and (W/L)
B
The sizes can also be chosen by using the design value of
V
L
and using the following equation:
( ) ( )
DS TN GS
S
n DS DS TN GS
S
n D
v V v
L
W
K v v V v
L
W
K i
|
.
|

\
|
~
|
.
|

\
|
=
' '
5 . 0
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 46
NAND Gate Device Size Selection
(continued)
Two sources of error that arise are the facts that
V
SB
and V
GS
of the two transistors do not equal.
These factors should be considered for proper gate
design

The technique used to calculate the size of the load
transistor for the depletion-mode load inverter is
the exact same as for this NAND gate
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 47
Layout of the NMOS Depletion-Mode
NOR and NAND Gates
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 48
Complex NMOS Logic Design
An advantage of NMOS technology is that it is simple to design
complex logic functions based on the NOR and NAND gates
The circuit in the
figure has the logic
function:
Y = A + BC + BD

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 49
Complex Logic Gate Transistor Sizing
There are two ways to find the W/L ratios of the
switching transistors

1) Using the worst case (longest) path and choosing the
W/L ratio such that the R
ON
of the multiple legs match
similar to the technique used to find the W/L ratios in
the NAND Gate

2) Partitioning the circuit into series sub-networks, and
make the equivalent on-resistances equal

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 50
Complex Logic Gate Transistor Sizing
The figure on the left
shows the worst case
technique to find the
sizes where
(W/L)
S
=2.06 is the
reference inverter ratio
for this technology and
the longest path is 3
transistors are in series

The figure on the right
shows the partitioning
technique to find the
sizes which gives two
4.12/1 ratios in series
which is 2(2.06/1)


Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 51
Static Power Dissipation
Static Power Dissipation is the average power
dissipation of a logic gate when the output is in both
the high and low states


I
DDH
= current in the circuit for v
O
= V
H

I
DDL
= current in the circuit for v
O
= V
L

Since I
DDH
= 0 A for v
O
= V
H
:
2
DDL DD DDH DD
av
I V I V
P
+
=
2
DDL DD
av
I V
P =
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 52
Dynamic Power Dissipation
Dynamic Power Dissipation is the power
dissipated during the process of charging and
discharging the load capacitance connected to the
logic gate
Discharging
Charging
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 53
Dynamic Power Dissipation
Based on the energy equation, the energy delivered to
the capacitor can be found by:


The energy stored by the capacitor is:


The energy lost in the resistive elements is given by:


2
) (
) 0 ( 0
) ( ) (
DD
V
V
C DD DD D
CV dv t i V C dt t i V E
C
C
= = =
} }

2
2
DD
D
CV
E =
2
2
DD
S D L
CV
E E E = =
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 54
Dynamic Power Dissipation
The total energy lost in the first charging and
discharging of the capacitor through resistive elements
is given by:


Thus it can be seen that for every cycle (frequency)
that the gate is changed, the dynamic power
dissipation is given by:
2
2 2
2 2
DD
DD DD
TD
CV
CV CV
E = + =
f CV P
DD D
2
=
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 55
Power Scaling in MOS Logic
By reducing the W/L of the load and switching
transistors of an inverter, it is possible to reduce
the power dissipation by the same factor without
sacrificing V
H
and V
L
. This same concept works
for increasing the power which will increase the
dynamic response.
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 56
Power Scaling in MOS Logic
a) Original Saturated Load Inverter
b) Saturated Load inverter designed to operate at 1/3 the power
c) Original Depletion-Mode Inverter
d) Depletion-mode inverter designed to operate at twice the power

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 57
Dynamic Behavior
Capacitance in MOS Logic Circuits
The MOS device has the
capacitances C
SB
, C
GS
, C
DB
,
and C
GD
that need to be
considered for dynamic
response analysis, but
depending on the
configuration, some of them
will be shorted out as seen in
the first figure

The capacitance seen at a
node can be lumped together
as seen in the second figure
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 58
Fan-out Limitations
Static design constraints are not usually important
for MOS logic circuits since they normally drive
capacitive loads (i.e. the gate of a MOS)
As the number of gates the output (fan-out) of a
logic device has to drive, the load capacitance
increases, and the time response decreases
This notion implies that the fan-out that a logic
circuit can drive will be limited to time delay
tolerances of the circuit
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 59
Dynamic Response of the NMOS
Inverter with a Resistive Load
The rise and fall times and propagation delays are
given by the relationships:



where R and C are the resistance and capacitance
seen at the output
RC
RC t t
PHL PLH
f r
69 . 0
2 . 2
= =
= =
t t
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 60
Dynamic Response of the NMOS
Inverter with a Resistive Load
There are four
important times
that need to be
considered when
characterizing the
dynamic response
of a logic circuit
which are denote
t
1
t
4
in the figure


Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 61
Dynamic Response of the NMOS
Inverter with a Resistive Load
It is also possible to calculate
PHL
and t
f
by a
piecewise analysis technique, and are given by the
following equations:
(
(

|
|
.
|

\
|
|
|
.
|

\
|

A
+
A
A +
= =

)
`

+
(

|
|
.
|

\
|
+

= + = =
TNS H
TNS
H
TNS H
onS f
TNS H
TNS
L H
TNS H
onS PHL
V V
V V
V V
V V V
C R t t t
V V
V
V V
V V
C R t t t t
1 . 0 2
2
9 . 0
9 . 0 2
ln
2
1 4 ln ) (
1 4
2 2 3 3
t
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 62
NMOS Inverter with a Depletion-Mode
Load Dynamic Response
Just as in the resistive
load inverter, the
depletion-mode load
inverter has the same
dynamic response
characteristics that need
to be considered, and
has four times that
needed for calculations
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 63
NMOS Inverter with a Depletion-Mode
Load Dynamic Response
The following are the basic equations for calculating
dynamic response characteristics

( )
( )
( )
)
`

A +
+
(

|
.
|

\
|
A
= =
(
(

|
|
.
|

\
|
|
|
.
|

\
|

A
+
A
A +
=

+
+
(

|
|
.
|

\
|

= + =

)
`

+
(

|
|
.
|

\
|
+

= + = =
TNL
L TNL H TNL
onL r
TNS H
TNS
H
TNS H
onS f
TNL
L TNL H
L H
TNL
onL PLH
TNS H
TNS
L H
TNS H
onS PHL
V
V V V V
V
V
C R t t t
V V
V V
V V
V V V
C R t
V
V V V
V V
V
C R t t t
V V
V
V V
V V
C R t t t t
1 . 0
2 1
20
ln
1 . 0 2
2
9 . 0
9 . 0 2
ln
2 1 4 ln
2
1 4 ln ) (
1 4
2 2 3
2 2 3 3
t
t
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 64
NMOS Inverter with a Depletion-Mode
Load Dynamic Response Example
Find t
f
, t
r
,
PHL
,
PLH
and
p
for a depletion-mode
load inverter where:
(W/L)
S
= 2.06/1 and (W/L)
L
= 1/2.15
C
LOAD
= 0.1 pF
V
TNS
= 1 V and V
TNL
= -3 V
V
DD
= 5 V and V
L
= 0.25 V
K
S
= (2.06)(25 10
-6
A/V
2
)
K
L
= (25 10
-6
A/V
2
)/2.15
Neglect body effect

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 65
NMOS Inverter with a Depletion-Mode
Load Dynamic Response Example
First find the on-resistances of the two NMOS
( )
( ) ( )
( )
( )
O =
|
.
|

\
|
=

=
O =

|
.
|

\
|
=

=
k
V
A
V K
R
k
V
A
V V K
R
TNL L
onL
TNS H S
onS
7 . 28
3
15 . 2
25
1 1
85 . 4
1 5 25 06 . 2
1 1
2
2

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 66
NMOS Inverter with a Depletion-Mode
Load Dynamic Response Example
It is now possible to calculate the propagation
delays
( )
ns
ns pF k
V
V V V
V V
V
C R
ns pF k
V V
V
V V
V V
C R
PHL PLH
p
PLH
TNL
L TNL H
L H
TNL
onL PLH
PHL
TNS H
TNS
L H
TNS H
onS PHL
58 . 2
2
56 . 4 ) 59 . 1 )( 1 . 0 )( 7 . 28 (
2 1 4 ln
590 . 0 ) 22 . 1 )( 1 . 0 )( 85 . 4 (
2
1 4 ln
=
+
=
= O =

)

+
+
(

|
|
.
|

\
|

=
= O =

)
`

+
(

|
|
.
|

\
|
+

=
t t
t
t
t
t
t
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 67
NMOS Inverter with a Depletion-Mode
Load Dynamic Response Example
( )
ns pF k t
V
V V V V
V
V
C R t
ns pF k t
V V
V V
V V
V V V
C R t
r
TNL
L TNL H TNL
onL r
f
TNS H
TNS
H
TNS H
onS f
47 . 9 ) 03 . 3 )( 1 . 0 )( 7 . 28 (
1 . 0
2 1
20
ln
25 . 1 ) 57 . 2 )( 1 . 0 )( 85 . 4 (
1 . 0 2
2
9 . 0
9 . 0 2
ln
= O =
)
`

A +
+
(

|
.
|

\
|
A
=
= O =
(
(

|
|
.
|

\
|
|
|
.
|

\
|

A
+
A
A +
=
The rise and fall times can be calculated in the following
manner
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 68
NMOS Inverter with a Saturated Load
Dynamic Response
The following are the basic equations for calculating
dynamic response characteristics and can be used in a
similar manner as the previous example

C R t
V V
V V
V V
V V V
C R t
C R
V V
V
V V
V V
C R
onL r
TNS H
TNS
H
TNS H
onS f
onL PLH
TNS H
TNS
L H
TNS H
onS PHL
9
160
1 . 0 2
2
9 . 0
9 . 0 2
ln
2
2
1 4 ln
=
(
(

|
|
.
|

\
|
|
|
.
|

\
|

A
+
A
A +
=
=

)
`

+
(

|
|
.
|

\
|
+

=
t
t
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 69
Comparison of Load Devices
The current has
been normalized
to 50 Afor
v
o
=V
OL
=0.25V
isthefigurefor
thevarious
typesof
inverters
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 70
Comparison of Load Devices
Body effect degrades the performance of the load
device
The saturated load devices have the poorest
PLH

since they have the lowest load current delivery
The saturated load devices also reach zero current
before the output reaches 5 V
The linear load device is faster than the saturated
load device, but still slower than the resistive load
inverter.
The fastest
PLH
is from the depletion-mode device

Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 71
Comparison of Load Devices
Simulated fall times for a
0.1 pF load
Simulated rise times for
a 0.1 pF load
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 72
Propagation Delay Design Example
Design depletion-mode load inverter with a
propagation delay (
P
) of 2 ns, and find (W/L)
S
,
(W/L)
L
t
f
, and t
r
such that:
C
LOAD
= 10 pF
V
TNS
= 1 V and V
TNL
= -3 V
V
DD
= 5 V, V
H
= 5 V and V
L
= 0.25 V
Base on a reference inverter with:
(W/L)
S
= 2.06/1
(W/L)
L
= 1/2.15
Use equations from Table 6.14


Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 73
Propagation Delay Design Example
( )
( )
1
266
43 . 4
1
1 . 60
25
10 503 . 1
10 503 . 1
) 3 0 (
6 . 1
) 1 5 ( 43 . 4
2 . 1
) 2 ( 2
10
43 . 4
43 . 4 ) 15 . 2 ( 06 . 2
6 . 1 2 . 1
2 2
6 . 1 2 . 1
2
2
3
2
3
=
|
.
|

\
|
=
|
.
|

\
|
=

=
|
.
|

\
|
=
(

+
+

=
= = =
(
(
(
(

=
+
=

L S L
L
S
L
L
S
TNL GSL
TNS H
L
S
L
onL onS
p
L
W
L
W
V
A
V
A
L
W
V
A
ns
pF
K
K
K
K
K
V V
V V
K
K
K
C C R C R

t
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 74
Propagation Delay Design Example
( )( )
( )( )
ns
V V K
L
W
C
t
ns
V V K
L
W
C
t
TNS H S
S
f
TNL GSL L
L
r
977 . 0
6 . 2
32 . 7
3 . 3
=

|
.
|

\
|
=
=

|
.
|

\
|
=
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 75
Propagation Delay Design Example
Repeat the example, but use Table 6.16 to include
body effect
First a scaling factor is needed to match this
design problems specifications

155
1 . 0
10
2
1 . 3
1
2
2
1
=
|
|
.
|

\
|
|
.
|

\
|
=
|
|
.
|

\
|
|
|
.
|

\
|
=
pF
pF
ns
ns
C
C
P
P
t
t
o
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 76
Propagation Delay Design Example
ns
ns
ns
ns
t
t
t t
ns
ns
ns
ns
t
t
t t
L
W
L
W
L
W
L
W
P
P
f f
P
P
r r
L L
S S
97 . 0
1 . 3
2
5 . 1
4 . 8
1 . 3
2
13
1
1 . 72
15 . 2
1
155
1
319
1
06 . 2
155
1
2
1 2
1
2
1 2
1 2
1 2
=
|
.
|

\
|
=
|
|
.
|

\
|
=
=
|
.
|

\
|
=
|
|
.
|

\
|
=
=
|
.
|

\
|
=
|
.
|

\
|
=
|
.
|

\
|
=
|
.
|

\
|
=
|
.
|

\
|
=
|
.
|

\
|
o
o
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 77
PMOS Logic
PMOS logic circuits predated NMOS logic circuit, but
were replaced since they are usually operate at slower
speeds (note the change in the power supplies)
Resistive Load Saturated Load Linear Load Depletion-mode Load
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 78
PMOS NAND and NOR Gates
NOR Gate NAND Gate
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 79
Silicon Art
In the earlier days of IC design, chip designers
were allowed to artistically express themselves on
the wafer by creating images with various
processing steps
However, todays modern foundries have stopped
this since the graphics did not pass the design
rules and were causing fabrication problems
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 80
Silicon Art Examples
Jaeger/Blalock
9/25/03
Microelectronic Circuit Design
McGraw-Hill
Chap 6 - 81
End of Chapter 6