Memory Designing In Verilog

ByUjash Poshiya

General Concepts
A memory is an array of storage locations
-Each

m bits
0 1 2 3 4 5 6

with a unique address Like a collection of registers, but with optimized implementation

Address is unsigned-binary encoded

-n address bits 2^n locations

2n2 2n1

If all locations are same size then total memory size

-2^n m bit memory

Memory Modeling
To help modeling of memory, Verilog provides support for two dimensions arrays. Behavioral models of memories are modeled by declaring an array of register variables; any word in the array may be accessed using an index into the array. A temporary variable is required to access a discrete bit within the array.

 Syntax:-

reg [wordsize:0] array_name [0:arraysize]

Examples:-

Declaration of memory :reg [7:0] my_memory [0:255];

Here [7:0] is the memory width and [0:255] is the memory depth with the following parameters: Width : 8 bits, little endian.

Depth : 256, address 0 corresponds to location 0 in the array.

Storing Values :my_memory[address] = data_in;

Reading Values :data_out = my_memory[address]; Bit Read:Sometimes there may be need to read just one bit. Unfortunately Verilog does not allow to read or write only one bit: the workaround for such a problem is as shown below. data_out = my_memory[address];

data_out_it_0 = data_out[0];

Memory Types
1)Volatile memory:Volatile means that all data is lost when The chip is power down. ExRAM,SRAM,on-chip memory. 2)Non Volatile memory:It retains data even when not powered. ExROM, Flash Memory

Types Of RAM
SRAM:Static RAM (SRAM) has the advantage of being faster than
DRAM, although the disadvantage is that it is more expensive. Power requirement of SRAM is low,but it depends on the clock speed.

DRAM:Dynamic RAM is less expensive, and therefore it is the most widely used .It uses less area on the chip.

Its disadvantage is that it uses more power than SRAM.

ROM
It is a non volatile memory. ROMs have traditionally been used in computer systems to store configuration data, such as bootstrap or BIOS code, which requires fast access. There are many types of ROM. EX- Mask ROM, PROM, EPROM, EEPROM

Flash Memory
It is same as EEPROM, which can be electrically erased and reprogrammed. Although flash memory is erased only one block or page at a time. it is much less expensive than EEPROM. This has made it the most popular form of non-volatile, solid-state storage. It has been wildly successful in consumer devices,such as music players, digital cameras, and game consols.

Basic Memory Operations

address inputs: - unsigned address d_in and d_out:-Type depends on application.

Write operation:en = 1, wr = 1; d_in value stored in location given by address inputs.

Read operation:-en = 1, wr = 0;
d_out driven with value of location given by address inputs.

Idle: en = 0

How To Initialize Memory?

By reading memory data patterns from a specified disk file. 1)Used for simulation. 2)Used in test benches. There are two Verilog functions are available:1. $readmemb (filename, memname, startaddr, stopaddr):-

-To read the data in the binary format.

2. $readmemh (filename, memname, startaddr, stopaddr):-To read the data in hexadecimal format.

Single Port SRAM

It include 4 inputs and a single data output line.
Inputs:1)Data input line 2)Address line 3)Clock input 4)Write enable
Ouput:- Output Data

Single Port Ram In No Change Mode

module ram(q,in,clk,we,en,add); // module name and inputs with output. output reg [3:0]q; // 4 bit output input clk,we,en; // we is write enable input and en is for enable the ram operation input [4:0]add; // address length input [3:0]in; // 4 bit input data reg [3:0] mem[31:0]; // memory declaration always@(clk) begin if(en) // enableing ram begin if (we) begin mem[add] <= in; end else q <= mem[add]; end end endmodule

//when write is enable

// write into memory

// when read mode is on // read from memory.

Output Of an RAM In No change

Single Port Syncronized RAM With Seperate Read And Write Address
-It is same as syncronus RAM but it is provided with enable input and also seperate read address input.

Verilog Code For SSRAM

Module ram_infr( input [7:0] data, input [5:0] read_addr, write_addr, input we, clk, output reg [7:0] q ); // Declare the RAM variable reg [7:0] ram[63:0]; always @ (posedge clk) begin // Write if (we) ram[write_addr] <= data; // Read (if read_addr == write_addr, return OLD data).To return // NEW data, use = (blocking write) rather than <= (non-blocking write) // in the write assignment. (NEW data may require extra bypass // logic around the RAM). q <= ram[read_addr]; end endmodule

Dual Clock SRAM With Seperate Read And Write Operation

It is same as above SRAM but it is provided with different read and write clock.

Verilog Code For Dual clock Ram

module ram_dual ( input [7:0] data, input [5:0] read_addr, write_addr, input we, read_clock, write_clock, output reg [7:0] q ); // Declare the RAM variable reg [7:0] ram[63:0]; always @ (posedge write_clock) begin // Write if (we) ram[write_addr] <= data; end always @ (posedge read_clock) begin // Read q <= ram[read_addr]; end endmodule

True Dual Port SRAM

It has two input data port as well as two output ports with seperate write enable inputs. It also has separate address Line.

Code For Dual Port RAM

module true_dpram_sclk ( input [7:0] data_a, data_b, input [5:0] addr_a, addr_b, input we_a, we_b, clk, output reg [7:0] q_a, q_b ); // Declare the RAM variable reg [7:0] ram[63:0];

// Port A always @ (posedge clk) begin if (we_a) begin ram[addr_a] <= data_a; q_a <= data_a; end else begin q_a <= ram[addr_a]; end end

Continue
// Port B
always @ (posedge clk) begin if (we_b) begin ram[addr_b] <= data_b; q_b <= data_b; end else begin q_b <= ram[addr_b];

end
end

endmodule

Code For Simple ROM

module rominfr (clk, en, addr, data); input input clk; en;

input [4:0] addr; output reg [3:0] data; always @(posedge clk)

begin
if (en) case(addr) 4b0000: data <= 4b0010; 4b0001: data <= 4b0010; 4b0010: data <= 4b1110; 4b0011: data <= 4b0010;

4b0100: data <= 4b0100;

Continue
4b0110: data <= 4b1100; 4b0111: data <= 4b0000;

4b1000: data <= 4b1010;

4b1001: data <= 4b0010; 4b1010: data <= 4b1110; 4b1011: data <= 4b0010; 4b1100: data <= 4b0100; 4b1101: data <= 4b1010; 4b1110: data <= 4b1100;

4b1111: data <= 4b0000;

default: data <= 4bXXXX; endcase end endmodule

Output