Delays in Verilog

Presented BY: Shashank Mistry Subhash Pakki Jitu Mistry

Delays in Verilog

Why delays and timing so important ?

They allow a degree of realism to be incorporated into the modeling process.

The time taken for changes to propagate through a module may lead to race conditions in other modules.

Some designs, such as high speed microprocessors, may have very tight timing requirements that must be met.

Types of Delays.

Depending on the design approach,

Gate-level Modeling Dataflow Modeling Behavioral Modeling

Gate level modelling

Propagation delay : Gate level modelling delay described below as: Rise Fall Min/Typ/Max values Turn-off

through the gate, and the time taken for the output to actually change state, according to input.

Rise delay
The rise delay is associated with a gate output transition to a 1 from another value(0,x,z).

Format: operation #( Rise_Val, fall_Val ) a1( out, i1,

i2);
Ex:

and #(1 , 0 ) a1(out ,i1,i2); //Rise=1, Fall=0, Turn-Off=0

Fall delay
The fall delay is associated with a gate output transition to 0 from another state 1

Format: operation #( Rise_Val, fall_Val ) a1( out, i1, i2); Ex:-> and #(0 , 1 ) a1(out ,i1,i2);
// Rise=0 Fall=1 Turn-Off=0

Turn-off delay
The turn-off delay is associated with a gate output transition to the high impedance value(z) from another value(0,1,x).
Rise Delay Fall Delay Turn-Off Delay 0,x,z -> 1 1,x,z -> 0 0,1,x -> z

If the value changes to x, the minimum of three delay is considered.

Number Of Delays 1
2

Specified delays Rise, fall and turn-off times of equal length

Rise and fall times

Rise, fall and turn off

Min, typ or max values

For each type of delay, there are three values, min,typ and max can be specified. Any one value can be chosen at the start of the simulation Because of IC fabrication process variations.

Ex: And #( 2:3:4, 3:4:5, 4:5:6) a ( out, i1, i2 );

#'num'
In Verilog delays can be introduced with #'num' as in the examples below, where # is a special character to introduce delay, and 'num' is the number of ticks simulator should delay current statement execution.

#1 a = b // Delay by 1, i.e. execute after 1 tick unit

#'num'
We can provide num value of different way by variable or/and parameter

Parameter

delata= 10; #delta out = in1& in2

Note: # There is no way we could synthesize delays, but of course we can add delay to particular signals by adding buffers.

Dataflow Modelling
As dataflow modelling use the concept of signals or values

The delays are associated with the Net (e.g. a Wire) along which the value is transmitted

Delays values control the time between the change in a right hand side operand and when the new value is assigned to the left hand side. a = b; means ab

Dataflow Modelling
Since values can be assigned to a net in a number of ways, there are corresponding methods of specifying the appropriate delays.

Regular Assignment Delay 2.Net Declaration Delay 3.Implicit Continuous Assignment

1.

Regular Assignment Delay

To assign a delay in continuous assignment the delay value is specified after the keyword assign. This is used to introduce a delay onto a net that has already been declared.

e.g. wire out;

assign #10 out = in1 & in2;

Net Declaration Delay

The Delay to be attributed to a Net can be associated when the Net is declared. e.g.

// net delays

wire #10 out; assign out = in1 & in2; // the same effect as the following, generally preferable wire out; assign #10 out = in1 & in2;

Implicit Continuous Assignment

Since a net can be implicitly assigned a value at its declaration, it is possible to introduce a delay then, before that assignment takes place. E.g.

wire #10 out = in1 & in2; // same as

wire out; assign #10 out = in1 & in2;

DELAYS IN BEHAVIOURAL MODELLING

There are following method Delay-based timing control Regular Intra- assignment Zero delay

REGULAR DELAY CONTROL

Regular delay control is used when a non zero delay is specified to the left of a procedural assignment This is sometimes also referred to as interassignment delay control Example:#10 q = x+y; It simply waits for the appropriate number of timesteps before executing the command.

INTRA ASSIGNMENT DELAY

Instead of specifying delay control to the left of tha assignment, it is possible to assign a delay to the right of the assignment operator. Example: q = #10 x+y; With this kind of delay ,the value of x+y is stored at the time that the assignment is executed, but this value is not assigned to q until after the delay period.

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ZERO DELAY
Zero delay is a method to ensure that a statement is executed last,after all other statements in that simulation time are execcuted. This is to to elminate race arround conditions. However if there are multiple zero delay statements,the order between them is nondeterministic. EX:#0 x=1

SEQENTIAL BLOCKS
The keywords begin and end are used to group statements into seqential blocks. A statement is executed only after its preceeding statement completes execution.

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PARALLEL BLOCKS
Parallel blocks, specified by keywords fork and join,provide intresting simulation features. Statements in a parallel block are executed concurrently. Ordering of statements is controlled by delay or event control assigned to each statement.

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Setup and Holdtime

Very important in sequential logic.

$setup(data_line, clk_line, limit); $hold(clk_line, data_line, limit);

Thank you