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Mitchell Belser, P.E. Visiting Instructor Department of Computer Engineering Jackson State University mbelser@ieee.org
Schmitt Trigger
v-minus v-plus
R7
R10
R9 output
2
R8
2
V1
1
input
V2
1
R6
Thermionic Trigger
R12 Vin
U1 output
Q1 input
R4
R5
M5
M6 M4 GND
input
U1A
U3A
U4A
output
M2
VDD
M3 M1
GND
Applications
Input buffers for digital signals. Crystal oscillator circuits. Clean up noisy signals (switch debounce). Speed up signals with slow edges.
Specific Improvements
Innovation : A CMOS Schmitt trigger circuit containing additional test circuitry that allows trigger voltage levels to be detected at the input without needing to ramp the input voltage. Important components of innovation: The test circuitry consists of combinational logic and a CMOS switch. Digital input signals determine whether the high or low threshold voltage is measurable.
M6 M4 GND
input
U1A
U3A
U4A
output
M2
VDD
M3 M1
GND
Test
circuitry is shown in blue. Asserting test mode and vih input results in sout being shorted to the input. The gates of the feedback transistors are driven to vdd. The input is regulated to the high input threshold voltage VTH. Asserting test mode and vil input results in sout being shorted to the input. The gates of the feedback transistors are driven to gnd. The input is regulated to the low threshold voltage VTL. In normal operating mode the test circuitry has no effect on Schmitt trigger operation.
M5
U6A 7402N
U4A
output
Test_en
VTH
GND sout
Simply setting a digital input causes the threshold voltage to be present on the input pin of the Schmitt trigger. .
Simplifies test program and reduces test time resulting in increased profit margin.
Measurement Data
Part
C VCL-A4-5 5V
VDD VTH
4.21
STATIC VTL
2.92
RAMP VTH
4.2 4.24
Frequency
3.08 3.04 1.84 1.76 3.12 3.06 1.80 1.72 1 1k 1 1k 1 1k 1 1k
VTL
3.3 V
2.63
1.69
2.64 2.64
A VCL-A4-3
5V
4.22
2.98
4.24 4.28
3.3 V
2.64
1.73
2.66 2.64
Measurement Waveforms
VDD= 3.3V Ramp frequency = 1kHz
Summary
Schmitt trigger threshold test circuit. Measure rising and falling threshold levels. Ramping input and monitoring output state is no longer necessary. Reduction in test time. Increase in profit due to reduction in test time.