Advanced Computer Architecture

S1

Anant Gopal Joshi

Session 3 July 2012

Advanced Computer Architecture

July 2012

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Problem 1.6
Program Computer A Computer B Computer C Program 1 Program 2 Program 3 Program 4 Average 1000 1 2 10 253.25 100 10 1 1.25 28.0625 50 50 20 10 32.5

MIPS = (Number of Instructions / Time of Execution) / 1000000 For Program 1, Computer A MIPS = (1000000000 / 1 ) / 1000000 = 1000 For a Instruction mix of Program 1 Computer A performs best Average MIPS ranking is Computer A , Computer C and Computer B Computer C gives a uniform performance, Computer B comes next Computer A is some special purpose machine
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Problem 1.7
SIMD is a vector processor while MIMD is multiprocessor organization SIMD executes one program MIMD executes multiple programs
Feature Structure Resource sharing Multiprocessor Close coupled Share Bus and Clock Share all the resources physically Multicomputer Loosely coupled Separate systems Share the resources logically

Inter Process Com

Shared memory

Message passing

UMA All the processors have Uniform memory to the memory in the system - all memory is global NUMA the processors have a local memory that is also part of shared global memory COMA is NUMA with all the memory as a cache memory NORMA is a multicomputer system. The processors do not have a global memory
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Problem 2.3
Part A and B See Table 2.1 on page 76

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Problem 2.3
Graph and string reduction Consider the expression E = (A + B) + (C + D) Write the string as = (E, + ( + (A, B), + (C, D)))

= E A
Advanced Computer Architecture July 2012

+ + B C
Anant Gopal Joshi

+ D
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Problem 2.4
S1 A=B+D S2 C=A*3 S3 A=A+C S4 E = A/2

Statement
S1 S2 S3 S4

Inputs
B, D A, 3 A, C A, 2

Outputs
A C A E

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Problem 2.4
S1 X = Sin (Y) S2
Z=X+W

S4 X = Cos (Z)

S3 Y = -2.5 * W

Statement
S1 S2 S3 S4

Inputs
Y X, W W, 2.5 Z

Outputs
X Z Y X

S1

S2 || S3

S4

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Problem 2.4
For I = 1 A2 = B0 + C1 For I = 2 A3 = B1 + C2

B1 = A1 * K

C1 = B1 - 1

B2 = A2 * K

C2 = B2 - 1

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Problem 3.4
Speedup Sn = (W1 + Wn) / (W1 + Wn / N) = Work done by one machine / Work done by all = ( + (1 - )*K) / ( + (1 - )) = K - C*(K-1) For = 0 For = 1 Sn = K Sn = 1

For calculating the mean = I do not know Average will be the integral of the speedup equation from a to b divided by the range (b-a)
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Problem 3.13
Problem for me. The concepts Ra, Rh, R1, R2 etc. are not known to me at this moment.

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Instruction pipeline
Fetch Decode Execute Write

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Instruction pipeline
Instruction pipeline cycle Instruction issue latency Instruction issue rate Instruction execution time

Base scalar machine

IIL = 1, IIR = 1, IET = 1
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Instruction pipeline
Fetch Decode Execute Write

0 1 2 3 4 5 6 7 Resource conflicts will prevent issuing of instructions reducing pipeline effect

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Instruction pipeline
Address PC

Data

IR ALU

Control Unit

PSW Register file

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Instructions some definitions

Instruction codes Memory references Address modes GPR General Purpose Registers HLL High Level Language HLL Features in Instructions Interrupts ISR Interrupt Service Routine Stack Pointer SP, Base Register BR JSR Jump to Sub Routine RTS Return from Subroutine
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Instructions
CISC Complex Instruction Set Computer RISC Reduced Instruction Set Computer Complex instructions take chip space and may be used occasionally Complex tasks done by series of simple instructions

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Instructions
Simplify processor design Simplify compiler design Fixed instruction format Simple addressing modes Larger register sets

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Instructions
Hardwired Microprogrammed

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CISC
Control Unit Instruction and Data Path

Cache

Micro programmed Control Memory Main Memory

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RISC
Hardware Control Unit Data Path

Instruction Cache

Data Cache

Main Memory

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RISC Vs CISC
CISC Architecture RISC Architecture

Large set of instructions variable formats Many Addressing Modes Less number of GPRs Larger and variable Cycles Per Instruction Micro coded Instruction Set
Advanced Computer Architecture July 2012

Small set of instructions fixed format Limited Addressing Modes Large number of GPRs Smaller and uniform Cycles Per Instruction Hardware Instruction set
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VAX 8600 Architecture

GPR General Purpose Registers

TLB Translation Look aside Buffer

Console Console Bus

Virtual Address Bus

Execution Unit ALU

Instruction Unit 16 GPRs Cache 16KB Memory and I/O Control TLB I/O Subsystem

Floating Point Unit

Control Memory
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Main Memory 8 MB
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Advanced Computer Architecture

MC68040 Microprocessor
Instruction Bus Convert Execute Decode Write back Floating Point Unit Instruction Fetch ATC Cache Address bus 32 bits Bus Controller

MMU Controller

EA Calculation
EA Fetch Execute

Instruction Memory Unit

MMU Controller

Data bus 32 bits

ATC Write back Integer Unit Data Bus

Advanced Computer Architecture July 2012 Anant Gopal Joshi

Cache Bus control signals

Data Memory Unit

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RISC advantages
Simple instructions Faster Instruction issue rate better pipeline effect Uses lesser resources Uses register files One memory operation at a time (Load or Store instructions) Lesser and simpler addressing modes Lesser chip density and area Better Cycles Per Instruction Simple instruction set helps optimizing compilers

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RISC disadvantages
Larger program size Complex operations are performed by use of software functions Good compiler support and standard function library required Compiler must be a good optimizing compiler

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RISC compiler specialities

Concept of cooperating procedures Concept of context frames Stacking of context and nesting of frames Sharing of registers in cooperating procedures In, Out, and Local registers of procedures and their sharing

Concept of context switching and stack operations

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