An enabled (gated) R-S latch

R Q R S Q Q S

Unclocked R-S Latch

En

R S

R S

Q Q

Output changes only when input changes, and enabled

R
Clock Signal Level-sensitive R-S Latch

Q
En Q

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Regular vs. Enabled R-S latches

Assume that latches have no time delay (ideal)

R S

R S

Q Q(regular) Q En

R S

R
S

Q Q(enabled)
En Q

S R En Q
(regular)

Set Reset

Set Reset

Set

Q
(enabled)

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Clocking an enabled R-S Latch

R
S Clock Clock
(En)

R S

Q Q
En Q

S
R Q

Set

Set Reset Reset

Set

A clocked R-S latch follows the R/S inputs when the clock is asserted. A clocked R-S latch stores the value when the clock goes low when the clock is not asserted.
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D-Latches (gated)
D C clk D R S Q
En Q

In a D-latch, the output follows the input when the clock is high.

When the clock is low, the output remains what it was on the falling edge of the clock.

clk

Clock D Q

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Edge-triggering
D The carrot symbol means edge-triggered Q clk
In a positive edge-triggered D FlipFlop, the output looks at the input only during the instant that the clock changes from low to high.

Clock D

Edge-triggered D Flip-flop: Every rising edge, output is set to the input

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Negative Edge-triggering
D Q
In a negative edge-triggered D FlipFlop, the output looks at the input only on the falling edge of the clock.

clk

Clock
D

Negative Edge-triggered D Flip-flop: Every falling edge, output is set to the input

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J-K Flip-Flops
We want to eliminate the forbidden state of the R-S Latch (when R and S are both 1). Alternative option: Q, Q are always different. Use them to control the input. R S Q Q clk Q

K J

Jt 0 0 0 0 1 1 1 1

Kt 0 0 1 1 0 0 1 1

Qt 0 1 0 1 0 1 0 1

Qt+1 0 1 0 0 1 1 1 0

Hold Reset Set Toggle J, K act just like Set and Reset, except: When theyre both 1, we get a toggle.

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Toggle Flip-Flops
Build a flip-flop that toggles its state on each clock edge when it is enabled (T is the enable). T Q Q T J K Q Q Q
Q+ is the Q output after the clock changes

Q
clk

T 0 0 1 1

Q 0 1 0 1

Q+ 0 1 1 0

Clock T Q

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Racing the clock

D
D Q

Real signals dont change instantly

Clk Clk D
D is changing during the rising edge of Clk. Is a 1 or 0 clocked in? D is changing right after the rising edge of Clk. Is a 1 or 0 clocked in?

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Setup and Hold Times

D
D Q

Setup Time: How long a signal must be stable preceding the clock edge Hold Time: How long a signal must be stable after the clock edge

Clk

setup hold time time Clk D

Setup: Pass Hold: Pass Setup: Fail Hold: Pass Setup: Pass Hold: Fail Setup: Fail Hold: Fail

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Setup and Hold times: Flip Flops

20ns 5ns 74LS74 Positive Edge Triggered D Flipflop 20ns 5ns

Clk D Q 23ns 40ns

Setup time 20ns Hold time 5ns Propagation delays - Low to High 23 ns - High to Low 40 ns
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Asynchronous flip-flop inputs

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The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous inputs because they have effect on the outputs (Q and not-Q) only in step, or in sync, with the clock signal transitions. These extra inputs that I now bring to your attention are called asynchronous because they can set or reset the flip-flop regardless of the status of the clock signal. Typically, they're called preset and clear

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Race Around Condition

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