Fabrication of MOSFETs

INTRODUCTION
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS Voltage applied to insulated gate controls current between source and drain

nMOS Transistor
Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor Gate and body are conductors SiO2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor
Source Gate Drain Polysilicon SiO2

n+ p

n+ bulk Si

nMOS Operation
Body is commonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF
Source Gate Drain Polysilicon SiO2
0

n+ p

n+
S D

bulk Si

nMOS Operation Cont.

When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON
Source Gate Drain Polysilicon SiO2
1

n+ p

n+
S D

bulk Si

0: Introduction

Slide 5

pMOS Transistor
Similarly Body tied to high voltage (VDD) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior
Source Polysilicon SiO2 Gate Drain

p+ n

p+ bulk Si

Transistors as Switches
We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain
g=0 d nMOS g s s d ON s s s d OFF s d OFF g=1 d ON

d pMOS g

N-MOS Fabrication Process

Si-substrate

Fig. (1) Pure Si single crystal

------------------------------------------------------------------------------------------------Fig. (2) P-type impurity is lightly doped

N-MOS Fabrication Process

Thick SiO2 (1 m)

------------------------------------------------------------------------------------------------Fig. (3) SiO2 Deposited over si surface

------------------------------------------------------------------------------------------------Fig. (4) Photoresist is deposited over SiO2 layer

Photoresist Thick SiO2 (1 m)

N-MOS Fabrication Process

UV Light

Mask-1 Photoresist

----------------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------------------

Thick SiO2 (1 m)

Mask-1 is used to expose the SiO2 where S, D and G is to be formed.

Fig. (5) Photoresist layer is exposed to UV Light through a mask

N-MOS Fabrication Process

Polymerised Photoresist

----------------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ---------------------------------Thick SiO2 (1 m)

Fig. (6) Developer removes unpolymerised photoresist. It will cause no effect on Si surface

N-MOS Fabrication Process

----------------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------------------

Thick SiO2 (1 m)

Fig. (7) Etching [HF acid is used] will remove SiO2 layer which is in direct contact with etching solution

N-MOS Fabrication Process

----------------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------------------

Thick SiO2 (1 m)

Fig. (7) unpolymerised photoresist is also etched away [using H2SO4]

N-MOS Fabrication Process

Thin SiO2 (0.1 m) Thick SiO2 (1 m)

----------------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------------------

Fig. (8) A thin layer of SiO2 grown over the entire chip surface

N-MOS Fabrication Process

Polysilicon layer (1 2 m)

----------------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ---------------------------------Thick SiO2 (1 m) Thin SiO2 (0.1 m)

Fig. (9) A thin layer of polysilicon is grown over the entire chip surface to form GATE

N-MOS Fabrication Process

Photoresist

Polysilicon layer

----------------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ---------------------------------Thick SiO2 (1 m)

Thin SiO2 (0.1 m)

Fig. (10) A layer of photoresist is grown over polysilicon layer

N-MOS Fabrication Process

UV Light

Mask-2

----------------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ---------------------------------Mask-2 is used to deposit Polysilicon to form gate. Fig. (11) Photoresist is exposed to UV Light

N-MOS Fabrication Process

Polysilicon

Thin SiO2 (0.1 m) Thick SiO2 (1 m)

----------------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------------------

Fig. (12) Etching will remove that portion of Thin SiO2 which is not exposed to UV light

N-MOS Fabrication Process

Polysilicon used as GATE (1 2 m)

Thin SiO2 (0.1 m) Thick SiO2 (1 m)

----------------------------------------------------------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ----------------------------------

Fig. (13) Polymerised photoresist is also stripped away

N-MOS Fabrication Process

GATE SOURCE DRAIN

Thin SiO2 (0.1 m) Thick SiO2 (1 m)

- - - - - - - - - - - - - ------ - - - - - - -- ---- - - - - - ------------------ ----- ------------ - - - - - - - - - - - - - - n+ - - - - - - - - -n+ ------------------------------------------

Fig. (14) n+ Doping to form SOURCE and DRAIN

N-MOS Fabrication Process Step - Metallization

- - - - - - - - - - - - - ------ - - - - - - -- ---- - - - - - ------------------ ----- ------------ - - - - - - - - - - - - - - n+ - - - - - - - - -n+ -----------------------------------------Thick SiO2 (1 m) Thick SiO2 (1 m)

Fig. (15) A thick layer of SiO2 (1 m) is again grown.

N-MOS Fabrication Process Step - Metallization

UV Light

Mask-3

Mask-3 is used to make contact cuts for S, D and G. Photoresist

- - - - - - - - - - - - - ------ - - - - - - -- ---- - - - - - ------------------ ----- ------------ - - - - - - - - - - - - - - n+ - - - - - - - - -n+ -----------------------------------------Thick SiO2 (1 m) Thick SiO2 (1 m)

Fig. (16) Photoresist is grown over thick SiO2. Selected areas of the poly GATE and SOURCE and DRAIN are exposed where contact cuts are to be made

N-MOS Fabrication Process Step - Metallization

Mask-3

Photoresist

- - - - - - - - - - - - - ------ - - - - - - -- ---- - - - - - ------------------ ----- ------------ - - - - - - - - - - - - - - n+ - - - - - - - - -n+ -----------------------------------------Thick SiO2 (1 m) Thick SiO2 (1 m)

Fig. (17) The region of photoresist which is not exposed by UV light will become soft. This unpolymerised photoresist and SiO2 below it are etched away.

N-MOS Fabrication Process Step - Metallization

Mask-3 Photoresist

- - - - - - - - - - - - - ------ - - - - - - -- ---- - - - - - ------------------ ----- ------------ - - - - - - - - - - - - - - n+ - - - - - - - - -n+ -----------------------------------------Thick SiO2 (1 m) Thick SiO2 (1 m)

Fig. (18) The contact cuts are formed for S, D and G (hardened photoresist is stripped away).

N-MOS Fabrication Process Step - Metallization

Metal (1m)

- - - - - - - - - - - - - ------ - - - - - - -- ---- - - - - - ------------------ ----- ------------ - - - - - - - - - - - - - - n+ - - - - - - - - -n+ -----------------------------------------Thick SiO2 (1 m) Thick SiO2 (1 m)

Fig. (19) Metal (aluminium) is deposited over the surface of whole chip (1 m thickness).

N-MOS Fabrication Process Step - Metallization

Photoresist

Metal (1m)

- - - - - - - - - - - - - ------ - - - - - - -- ---- - - - - - ------------------ ----- ------------ - - - - - - - - - - - - - - n+ - - - - - - - - -n+ -----------------------------------------Thick SiO2 (1 m) Thick SiO2 (1 m)

Fig. (20) Photoresist is deposited over the metal.

N-MOS Fabrication Process Step - Metallization

UV Light

Mask-4
Photoresist

Metal (1m)

- - - - - - - - - - - - - ------ - - - - - - -- ---- - - - - - ------------------ ----- ------------ - - - - - - - - - - - - - - n+ - - - - - - - - -n+ -----------------------------------------Thick SiO2 (1 m) Thick SiO2 (1 m)

Mask-4 is used to deposit metal in contact cuts of S, D and G. Fig. (21) UV Light is passed through Mask-4 (with a aim of removing all metal other than metal in contact-cuts).

N-MOS Fabrication Process Step - Metallization

Mask-4
Photoresist

Metal (1m)

- - - - - - - - - - - - - ------ - - - - - - -- ---- - - - - - ------------------ ----- ------------ - - - - - - - - - - - - - - n+ - - - - - - - - -n+ -----------------------------------------Thick SiO2 (1 m) Thick SiO2 (1 m)

Fig. (22) Photoresist and metal which is not exposed to UV light are etched away.

N-MOS Fabrication Process Step - Metallization

SOURCE GATE DRAIN

- - - - - - - - - - - - - ------ - - - - - - -- ---- - - - - - ------------------ ----- ------------ - - - - - - - - - - - - - - n+ - - - - - - - - -n+ ------------------------------------------

Fig. (23) Final n-MOS Transistor

Fabrication Steps-CMOS
Start with blank wafer First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2

p substrate

Oxidation
Grow SiO2 on top of Si wafer 900 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

Photolithography

Exposure Processes

Photoresist
Used for lithography . Lithography is a process used to transfer a pattern to layer on the chip. Similar to Printng Process Spin on photoresist (about 1 mm thickness) Photoresist is a light-sensitive organic polymer

Photoresist SiO2

p substrate

Lithography
Expose photoresist through n-well mask Strip off exposed photoresist

Photoresist SiO2

p substrate

Etch
Cluster Tool Configuration Wafers Etch Chambers Transfer Chamber Loadlock

RIE Chamber

Gas Inlet Wafer RF Power

Die-electric Etch Plasma Etch

Transfer Chamber

Exhaust

Etch
Etch oxide with hydrofluoric acid (HF) Only attacks oxide where resist has been exposed

Photoresist SiO2

p substrate

Strip Photoresist
Strip off remaining photoresist

SiO2

p substrate

n-well
n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si
SiO2 n well

Strip Oxide
Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

n well p substrate

Polysilicon
Deposit very thin layer of gate oxide < 20 (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor
Polysilicon Thin gate oxide n well p substrate

Polysilicon Patterning
Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon Thin gate oxide n well p substrate

Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact

n well p substrate

N-diffusion
Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing

n+ Diffusion

n well p substrate

N-diffusion cont.
Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

n+

n+ n well p substrate

n+

N-diffusion cont.
Strip off oxide to complete patterning step

n+

n+ n well p substrate

n+

P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

p+ Diffusion

p+

n+

n+ p substrate

p+ n well

p+

n+

Contacts
Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

Contact

Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

Metalization
Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

Metal

Metal Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

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