Async03 Tut Demo

Petrify: Method and Tool for Synthesis of Asynchronous Controllers and Interfaces
Jordi Cortadella (UPC, Barcelona, Spain), Mike Kishinevsky (Intel Strategic CAD Labs, Oregon), Alex Kondratyev (Berkeley Cadence Research Labs, CA), Luciano Lavagno (Politecnico di Torino, Italy ), Alex Yakovlev (University of Newcastle, UK)
Outline
Part 1: The Petrify Method
Overview of the Petrify synthesis flow Specification: Signal Tranistion Graphs State graph and next-state functions State encoding Implementation conditions Speed-independent circuits
Complex gates C-element architecture
ASYNC2003 - Tutorial on Petrify Method and Tool
Design flow
Specification (STG)
Reachability analysis
State Graph
State encoding
SG with CSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
ASYNC2003 - Tutorial on Petrify Method and Tool 3
Specification
x y
z
x
y z z+ x-
x+
y+
y-
z-
Signal Transition Graph (STG)

Token flow
x y z z+ x+ y+ yxz-
State graph
xyz 000
x+ z+
100
z+ x+ y+ y-
xzyx-
y+
101
y+
110 111
xz+
001
y+
011
z-
010
xyz 000
x+
x z (x y)
z+ x-
100
y+
y zx
z x y z
101
y+
110 111
xz+
y-
001
y+
011
z-
010
Gate netlist
x z (x y)
x y
y zx
z x y z
Design flow
Specification (STG)
State Graph
State encoding
SG with CSC
Logic decomposition
Technology mapping
Gate netlist
VME bus
Bus
DSr Data Transceiver LDS
LDTACK D DSr DSw DTACK DTACK LDS VME Bus Controller LDTACK D
Device
Read Cycle
10
STG for the READ cycle

DSr+ DTACK-
LDS+
LDTACK+
D+
DTACK+
DSr-
D-
LDTACK-
LDS-
D DSr DTACK VME Bus Controller
LDS
LDTACK
11
Choice: Read and Write cycles

DSr+ LDS+ LDTACK+ LDTACKD+ DTACK+ LDSDSrDDTACKDTACKDSw+ D+ LDS+ LDTACK+ DDTACK+ DSw12
LDTACK-
LDS-

LDTACK-
LDS-

LDTACK-
LDS-
Circuit synthesis
Goal:
Derive a hazard-free circuit under a given delay model and mode of operation
15
Speed independence
Delay model
Unbounded gate / environment delays Certain wire delays shorter than certain paths in the circuit
Conditions for implementability:

Consistency Complete State Coding Persistency
16
Design flow
Specification (STG)
State Graph
State encoding
SG with CSC
Logic decomposition
Technology mapping
Gate netlist
STG for the READ cycle

DSr+ DTACK-
LDS+
LDTACK+
D+
DTACK+
DSr-
D-
LDTACK-
LDS-
D DSr DTACK VME Bus Controller
LDS
LDTACK
18
Binary encoding of signals

DSr+
LDS+
DTACK-
LDTACKDSr+
LDTACKDTACK-
LDTACK-
LDTACK+
LDSDSr+
LDSDTACK-
LDS-
D+
DDTACK+ DSr-
19
Binary encoding of signals

10000
LDS+
DSr+
DTACK-
LDTACKDSr+
LDTACKDTACK-
LDTACK-
10010
LDTACK+
01100
LDS-
LDSDSr+
LDSDTACK-
10110
D+
01110
10110
00110
D-
DTACK+
DSr-
(DSr , DTACK , LDTACK , LDS , D)
20
Excitation / Quiescent Regions

ER (LDS+)
LDS+
QR (LDS-)
LDS-
LDS-
LDS-
QR (LDS+)
ER (LDS-)
21
Next-state function
01
LDS+
00
LDSLDS-
11
10110
LDS-
10
10110
22
Karnaugh map for LDS

LDS = 0
D LDTACK DTACK DSr
LDS = 1 10
D LDTACK DTACK DSr
00
01
11
00
01
11
10
00
00
01
01
1 0
11 10
11 10
- 0/1?
23
Design flow
Specification (STG)
State Graph
State encoding
SG with CSC
Logic decomposition
Technology mapping
Gate netlist
Concurrency reduction
DSr+
LDS+ DSr+
LDSDSr+
LDS-
LDS-
10110 10110
25
Concurrency reduction
DSr+
DTACK-
LDS+
LDTACK+
D+
DTACK+
DSr-
D-
LDTACK-
LDS-
26
State encoding conflicts
LDS+
LDTACK-
LDTACK+
LDS-
10110 10110
27
Signal Insertion
CSC+
LDS+
LDTACK-
LDTACK+
LDS-
101101 101100
D-
DSr-
CSC-
28
Design flow
Specification (STG)
State Graph
State encoding
SG with CSC
Logic decomposition
Technology mapping
Gate netlist
Complex-gate implementation
LDS D csc DTACK D D LDTACKcsc csc DSr (csc LDTACK )
Implementation conditions
Consistency
Rising and falling transitions of each signal alternate in any trace
Complete state coding (CSC)

Next-state functions correctly defined
Persistency
No event can be disabled by another event (unless they are both inputs)
Consistency + CSC + persistency
There exists a speed-independent circuit that implements the behavior of the STG
(under the assumption that ay Boolean function can be implemented with one complex gate)
Persistency
100
b+ a c b is this a pulse ? Speed independence glitch-free output behavior under any delay
a-
000
c+
001
b+
a c
a+
b+ a-
0000
a+
1000
b+
1100
a-
c+
d+ a+ b-
0100
c+
0110
d+ d-
0111
a+
1111
ba-
1011
c- a-
c-
ad-
c-
0011
1001
0001
ab cd
00 01 00 01 11 10
0000
a+
0 0 1
0 1
1000
b+
1100
a-
0100
ER(d+)
c+
11 10
1 1
0110
d+ d-
0111
a+
1111
ba-
1011
c- a-
c-
0011
ER(d-)
1001
0001
ab cd
00 01 00 01 11 10
0000
a+
0 0 1
0 1
1000
b+
1100
a-
0100
c+
11 10
1 1
0110
d+ d-
0111
a+
1111
d ad ac
Complex gate
ba-
1011
c- a-
c-
0011
1001
0001
Implementation with C elements

S
S+ z+ S- R+ z- R-
S (set) and R (reset) must be mutually exclusive S must cover ER(z+) and must not intersect ER(z-) QR(z-) R must cover ER(z-) and must not intersect ER(z+) QR(z+)
37
ab cd
00 01 00 01 11 10
0000
a+
0 0 1
0 1
1000
b+
1100
a-
0100
c+
11 10
1 1
0110
d+ d-
0111
a+
1111
b-
S R
ac
a-
1011
c- a-
c-
0011
1001
0001
0000
a+
1000
b+
1100
but ...
c
S R
a-
0100
c+
0110
d+ d-
0111
a+
1111
b-
ac
a-
1011
c- a-
c-
0011
1001
0001
Assume that R=ac has an unbounded delay Starting from state 0000 (R=1 and S=0):
a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ; R+ disabled (potential glitch)
0000
a+
1000
b+
1100
a-
0100
c+
0110
d+ d-
0111
a+
1111
b-
S R
ac
a-
1011
c- a-
c-
0011
1001
0001
ab cd
00 01 00 01 11 10
0000
a+
0 0 1
0 1
1000
b+
1100
a-
0100
c+
11 10
1 1
0110
d+ d-
0111
a+
1111
b-
S R
ab c
a-
1011
c- a-
c-
0011
1001
0001
Monotonic covers
C-based implementations
c
S R
ab c
c
c b a
weak
d a b
weak
d a
generalized C elements (gC)

Speed-independent implementations
Consistency Complete state coding Persistency
Circuit architectures
Complex (hazard-free) gates C elements with monotonic covers ...
Synthesis exercise
yz1001 yw0001 1011 w+
y+
1000
z-
w-
w+
w- z0000
x+
0011 x0111
1010
w- y+ 0010
0101 x+ z0100 z+
y+
x+
z+
x-
x+ y+ 0110
Derive circuits for signals x and z (complex gates and monotonic covers)
Synthesis exercise
wx
z00 01 11 10
1001
yw0001
1011 w+
yz
00 01
1
1 0 1
1 1 0 1
y+
1010
1000
w- z0000
x+
0011 x0111
0
0 0
w- y+ 0010
0101 x+ z0100 z+
11 10
x+ y+ 0110
Signal x
Synthesis exercise
wx
z00 01 11 10
1001
yw0001
1011 w+
yz
00 01
0 0 1 0
0 0
y+
1010
1000
w- z0000
x+
0011 x0111
0 1
0
w- y+ 0010
0101 x+ z0100 z+
11 10
1
1
x+ y+ 0110
Signal z
A simple filter: specification

Ain Rin IN
y := 0; loop x := READ (IN); WRITE (OUT, (x+y)/2); y := x; end loop
filter
Aout Rout OUT
47
A simple filter: block diagram
+ IN
Rin Ain
Rx
x
Ax Ry
y
Ay Ra Aa
OUT
control
Rout Aout
x and y are level-sensitive latches (transparent when R=1) + is a bundled-data adder (matched delay between Ra and Aa) Rin indicates the validity of IN After Ain+ the environment is allowed to change IN (Rout,Aout) control a level-sensitive latch at the output
A simple filter: control spec.

IN
Rin Ain Rx
x
Ax Ry
y
Ay Ra
+
Aa
OUT
control Rx+ Ax+ RxAxRy+ Ay+ RyAyRa+ Aa + Ra-
Rout Aout
Rin+
Rout+ Aout+ RoutAout49
Ain+
Rin-
Ain-
Aa-
A simple filter: control impl.

Rx Ax Ay Ry Ra Aa
Ain
Aout Rout
Rin
Rin+
Rx+
Ax+
Ry+ Ay+ RyAy-
Ra+ Aa+ RaAa-
Rout+ Aout+ RoutAout50
Ain+
Rin-
RxAx-
Ain-
Control: observable behavior

Rx Ax Ay Ry R a Aa
z Ain Rin
Aout C Rout
Rin+
AinRyA a+ zRout+
R x+
A x+
A aRinAout+
R aAin+ z+
AyR a+
A xRout-
R xAout-
Ay+ Ry+
51
Following slides borrowed from Ran Ginosar, Technion (VLSI Architectures course) with thanks
52
Generalized C Element
a b c
c b
+ C -
set(z) = ab reset(z) = b'c'
reset z
c c b a z b a b
reset
set z
c b a
a z
b a
set
set
reset
DYNAMIC (Pseudostatic)
STATIC
From Ran Ginosars course

STG Rules
Any STG:
Input free-choiceOnly inputs may control the choice) BoundedMaximum k (given bound) token per place Livenessevery signal transition can be activated
STG for Speed Independent circuits:

Consistent state assignmentSignals strictly alternate between + and PersistencyExcited non-input signals must fire, namely they cannot be disabled by another transition
Synthesizable STG:
Complete state codingDifferent markings must represent different states
We use the following circuit to explain STG rules:
req ack
REQ ACK
55
1-Bounded (Safety)
STG is safe if no place or arc can ever contain more than one token Often caused by one-sided dependency
req+ ack-
ack+ req-
REQ+ ACK-
ACK+ REQ-
STG is not safe: If left cycle goes fast and right cycle lags, then arc ack+ REQ+ accumulates tokens. (REQ+ depends on both ack+ and ACK- ) Possible solution: stop left cycle by right cycle
Liveness
STG is live if from every reachable marking, every transition can eventually be fired
reset-
reset_ok-
req+ ack-
ack+ req-
The STG is not live: Transitions reset, reset_ok cannot be repeated. But non-liveness is useful for initialization
Consistent state assignment

The following subgraph of STG makes no sense:
a+
a+
a-
a-
58
Persistency
STG is persistent if for all non-input transitions once enabled the transition cannot be disabled by another transitions. Non-persistency may be caused by arbitration or dynamic conflict relations STG must have places
ackreqreq+ ack+ REQ+ ACKACK+ REQ-
STG is not persistent: there is a place between req+ andack+ in which a token is needed in order to fire REQ+ . So there is some sort of nondeterminism either REQ+ manages to fire before ack+ or not Possible solution: introduce proper dependence of the left cylce on the right one (e.g., an arc from req+ to REQ+, and from REQ+ to ack+)
Complete State Coding

STG has a complete state coding if no two different markings have identical values for all signals.
req,ack,REQ,ACK:
ack0100
0000
req+ ack+
1000
1010
REQ+ ACK1000
ACK+
1011
reqcd\ab 00 00 01 11 10
REQ1001
1100
01
11
10
Disaster!
60
Complete State Coding

Possible solution: Add an internal state variable
req,ack,REQ,ACK,x:
ack-
req+
10000
10100
REQ+
ACK+
x-
x+
req-
ack+
11001 10001
ACK-
REQ-
61
A faster STG?
Does it need an extra variable?
req+ REQ+
ack+
ACK+
req-
REQ-
ack-
ACK62
STG specification in .astg format

.model simple_buffer .inputs r A .outputs a R .graph # left handshake (r,a) r+ a+ a+ rr- aa- r+ # right handshake (R,A) R+ A+ A+ RR- AA- R+ # interaction between handshakes r+ R+ A+ a.marking{<a-,r+><A-,R+>} .end
Drawn by draw_astg
64
The SG
req,ack,REQ,ACK: 0000 r+ 1000 R+ a+ 1100 1010 R+ ra+ 0100 1110 A+ R+ ar0110 1111 A+ ar0111 Ra0011 0101 Rr+ a1011 0001 RAa+ r+ 1111 1001 RAra+ 0111 1101 ARra0101 Aa-
A+
1011 Ra+ 1001 RAa+ 1101 1000 Ara+ 1100 Ar0100 a-
65
The SG
req,ack,REQ,ACK: 0000 r+ 1000 R+ a+ 1100 1010 R+ ra+ 0100 1110 A+ R+ ar0110 1111 A+ ar0111 Ra0011 0101 Rr+ a1011 0001 RAa+ r+ 1111 1001 RAra+ 0111 1101 ARra0101 Aa-
A+
1011 Ra+ 1001 Ra+ 1101 Ar1100 Ar0100 R+ a-
A1000 R+ a+ R+
CSC-conflict states are highlighted

66
Drawn by write_sg & draw_astg
67
Extra states inserted by petrify
68
Rearranged STG
req+ REQ+ ACK+ c2REQACKc2+ c0+
c1ack+ reqc1+ c0ack-
Initial Internal State: c0=c1=c2=1

The new State Graph
70
The Synthesized Complex Gates Circuit

INORDER = r A a R csc0 csc1 csc2; OUTORDER = [a] [R] [csc0] [csc1] [csc2]; [a] = a (csc2 + csc0) + csc1'; [R] = csc2 (csc0 (a + r) + R); [csc0] = csc0 (csc1' + a') + R' csc2; [csc1] = r' (csc0 + csc1); [csc2] = A' (csc0' (csc1' + a') + csc2);
71
Technology Mapping
INORDER = r A a R csc0 csc1 csc2; OUTORDER = [a] [R] [csc0] [csc1] [csc2]; [0] = R'; [1] = [0]' A' + csc2'; [a] = a csc0' + [1]; [3] = csc1'; [4] = csc0' csc2' [3]'; [5] = [4]' (csc1' + R'); [R] = [5]'; [7] = (csc2' + a') (csc0' + A'); [8] = csc0'; [csc0] = [8]' csc1' + [7]'; [csc1] = A' (csc0 + csc1); [11] = R'; [12] = csc0' ([11]' + csc1'); [csc2] = [12] (r' + csc2) + r' csc2;
# # # # # # # # # # # # # # gate gate gate gate gate gate gate gate gate gate gate gate gate gate inv: combinational oai12: combinational sr_nor: asynch inv: combinational nor3: combinational aoi12: combinational inv: combinational aoi22: combinational inv: combinational oai12: combinational rs_nor: asynch inv: combinational aoi12: combinational c_element1:asynch
72
The Synthesized Gen-C Circuit

INORDER = r A a R csc0 csc1 csc2; OUTORDER = [a] [R] [csc0] [csc1] [csc2]; [0] = csc0' csc1 (R' + A); [1] = csc0 csc2 (a + r); [2] = csc2' A; [R] = R [2]' + [1]; # mappable [4] = a csc1 csc2'; [csc0] = csc0 [4]' + csc2; # mappable [6] = r' csc0; [csc1] = csc1 r' + [6]; # mappable [8] = A' csc0' (csc1' + a'); [csc2] = csc2 R' + [8]; # mappable [a] = a [0]' + csc1'; # mappable
onto gC
onto gC onto gC onto gC onto gC
73
Petrify Environment
write_sg
STG
petrify
lib
SG
draw_astg
EQN
ps
74
Petrify
Unix (Linux) command line tool petrify h for help (flags etc.) petrify cg for complex gates petrify gc for generalized C-elements petrify tm for tech mapping draw_astg to draw write_sg to create state graphs Documented on line, including tutorial
75
References
See the attached Practical Exercise manual for various design examples using Petrify commands Additional references:
Petrify and all documentation can be downloaded from: http://www.lsi.upc.es/~jordic/petrify/petrify.html J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev, Logic Synthesis of Asynchronous Controllers and Interfaces, Springer, Berlin, 2002, ISBN3-540-43152-7
76

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Petrify: Method and Tool for Synthesis of Asynchronous Controllers and Interfaces

ASYNC2003 - Tutorial on Petrify Method and Tool

Signal Transition Graph (STG)

ASYNC2003 - Tutorial on Petrify Method and Tool

ASYNC2003 - Tutorial on Petrify Method and Tool

ASYNC2003 - Tutorial on Petrify Method and Tool

STG for the READ cycle

D DSr DTACK VME Bus Controller

ASYNC2003 - Tutorial on Petrify Method and Tool

Choice: Read and Write cycles

ASYNC2003 - Tutorial on Petrify Method and Tool

Choice: Read and Write cycles

ASYNC2003 - Tutorial on Petrify Method and Tool

Choice: Read and Write cycles

ASYNC2003 - Tutorial on Petrify Method and Tool

ASYNC2003 - Tutorial on Petrify Method and Tool

Conditions for implementability:

ASYNC2003 - Tutorial on Petrify Method and Tool

STG for the READ cycle

D DSr DTACK VME Bus Controller

ASYNC2003 - Tutorial on Petrify Method and Tool

Binary encoding of signals

ASYNC2003 - Tutorial on Petrify Method and Tool

Binary encoding of signals

(DSr , DTACK , LDTACK , LDS , D)

ASYNC2003 - Tutorial on Petrify Method and Tool

Excitation / Quiescent Regions

ASYNC2003 - Tutorial on Petrify Method and Tool

ASYNC2003 - Tutorial on Petrify Method and Tool

Karnaugh map for LDS

ASYNC2003 - Tutorial on Petrify Method and Tool

ASYNC2003 - Tutorial on Petrify Method and Tool

ASYNC2003 - Tutorial on Petrify Method and Tool

State encoding conflicts

ASYNC2003 - Tutorial on Petrify Method and Tool

ASYNC2003 - Tutorial on Petrify Method and Tool

Complete state coding (CSC)

Implementation with C elements

ASYNC2003 - Tutorial on Petrify Method and Tool

generalized C elements (gC)

A simple filter: specification

y := 0; loop x := READ (IN); WRITE (OUT, (x+y)/2); y := x; end loop

Aout Rout OUT

ASYNC2003 - Tutorial on Petrify Method and Tool

A simple filter: block diagram

A simple filter: control spec.

control Rx+ Ax+ RxAxRy+ Ay+ RyAyRa+ Aa + Ra-

Rout+ Aout+ RoutAout49

ASYNC2003 - Tutorial on Petrify Method and Tool

A simple filter: control impl.

Ry+ Ay+ RyAy-

Ra+ Aa+ RaAa-

Rout+ Aout+ RoutAout50

ASYNC2003 - Tutorial on Petrify Method and Tool

Control: observable behavior

ASYNC2003 - Tutorial on Petrify Method and Tool

ASYNC2003 - Tutorial on Petrify Method and Tool

set(z) = ab reset(z) = b'c'

From Ran Ginosars course

STG for Speed Independent circuits:

We use the following circuit to explain STG rules:

ASYNC2003 - Tutorial on Petrify Method and Tool

Consistent state assignment

ASYNC2003 - Tutorial on Petrify Method and Tool