Logic Modeling & Simulation

-- Satish Kumar Grandhi

Introduction
Logic Modeling techniques Objectives, Challenges Logic Simulator Classification Problems affecting Simulators

Nomenclature
Reconvergent Fan out
Different paths from the same signal

merging at some component

Level
Measure of the element distance

from the primary inputs Level of primary inputs is fixed to be 0 Level of an element I whose inputs come from element K1, K2, Ki
L(i) = 1 + max L (Kj)

Levels of Modeling
Refers to primitive component used

in the model Higher level model provides abstract view of system ; but involves loss of accuracy and detail Lower level model requires large computing resources; memory capacity, processing time Trade off : Complexity Vs Accuracy
Behavior Logic Gate Circuit HDL Languages Structural representation using primitive modules Timing information, Gates used to define all modules Tech. Data, device parameters,.

Binary Decision Diagrams (BDD)

Graph model of the function of a circuit Simple graph traversal determines the value of the output A . represents 0 ; otherwise 1

Sequential

Combinational

Any Difference ???

Constructing a BDD

Truth Tables and Cubes

F( n Variables) Table of 2n Entries
V -- > Table entry Z -- > Function V(2n 1) = Z(1,1,1.1)

Cube of a function represent a entry

in the truth table A cube of a function Z(x1, x2.) has the form (v1, v2,.| vZ) 00x|1 is a cube of the function Z and represents x1x2 implicant 00x|1 covers 000|1 & 001|1 If V= 010 , then Z = ?? { use intersection operator }

2. Primitive Cubes 1. Truth Table

3. Intersection Operator

Unknown Logic Value

Response of a sequential circuit depends on its initial state, usually

unpredictable Simulation algorithms use separate logic U to process unknown state turning it into 3 valued system {0 , 1, U}

Loss of information with 3 valued system ??

Issues with 3 Valued logic

Reconvergent fan-out results in pessimistic results Use of complementary unknown values U & U might help ?? NO Solution : Use several distinct unknown signals u1, u2, u3for every

variable such that Ui * Ui = 0 && Ui + Ui = 1 Highly Tedious

Logic Simulation
Methodology adopted to predict the behavior of a design prior to its

physical realization Ascertains that the design performs its specified behavior During the initial days (MSI era), prototypes were used for verification
Runs @ operating frequency Costly and Time consuming Lacks accuracy as models of ICs

Simulation replaces the prototype methodology

Higher Accuracy and easy analysis

Objectives
Design Verification (Pre-Silicon)
To find design errors Error space cannot be defined ; Hence, Fault coverage does not exist Generally, errors are related to data transfers and transformations rather

than the data operations itself

Manufactured IC Verification (Post-Silicon)
To detect physical faults Design errors are enumerable whose behavior is well defined Can Compute Fault Coverage

Challenges
Generating input stimuli Methodology to ascertain that results are correct How Good are the applied input stimuli ? In reality, Design Verification suffers from several limitations
Lack of formal procedures to generate tests Producing the stimuli is heuristic ; relying heavily on engineers intuition System that passes the test is correct only wrt the applied test Completeness of the tests cannot be promised

In spite of all these limitations, logic simulation is invaluable esp. for VLSI designs where prototypes are impractical

Simulator Classification
Terminology
Active signal

Activity
Event

Signals when changing their value @ arbitrary time Ratio of active signals to total number of signals { Generally, its max value is 5% origin for low power design concepts } Represents the change in the value of the signal

Simulators classification
Compiler Driven
Event Driven

Executes a compiled code model Executes based on active signals

Problems affecting Simulators

Treatment of unknown values

Delay Modeling
Hazard Detection Oscillation Control

Compiled Code Simulator

Code turns into simulator ; seeking inputs and flushing outputs Translate the logic network into a series of machine instructions

Assume timing values are intact (No setup or hold violations) ;

enables us to ignore delays Code model is generated such that preceding level signals are evaluated Parallel Pattern evaluation can be used for simultaneous evaluation ; works only for combinational

Note : Evaluates all signals for every input vector

Event Driven Simulator

An event-driven simulator monitors the occurrences of events Maintains an Activity list which determine which gates to evaluate

e =1 c =1 0 2 d=0 b =1 g
0 4 8

2
2

f =0

Time, t

Compiled Code Vs. Event Driven

Compiled-code
Cycle-based simulation High switching activity circuits Parallel simulation Limited by compilation times

Event-driven
Based on Signal Activity Implementing gate delays and detecting hazards Low switching activity circuits More complicated memory management

Gate Level Event Driven Simulator

Events scheduled to occur @ the

same time are stored in the same list

Time order is appropriately

Linked List used for Event Organization

maintained according to order .< tp < tq < tr < ..

An entry (I, Vi) associated with

time tq indicates that the value of signal I is set to Vi @ tq

Linked list also stores associated

delay values

Two Pass strategy

First, it retrieves the entries from

the event list and determines activated gates Then, it evaluates the activated gates and schedules their computed values

Issue

Due to (a,0) @4, (Z,0) is scheduled @ 12 But, Z is already set to zero @ 10

Modified.
Guaranteed to schedule true

events only Compares the new value Vj with the last scheduled value of j, denoted by lsv(j) Fewer schedule operations More memory to maintain last schedule events Efficiency depends on number of unnecessary events

One Pass strategy

Evaluates a gate as soon as it is

activated Avoids constructing the activated set a & b Scheduled to change @ same time If events are retrieved in the sequence
(b,0), (a,1)

Z is never

scheduled (a,1), (b,0) Z will under go both 0-1 & 1-0 transition, resulting in spike
Improvement : Cancel previously

Issue event if gate output is Scheduled scheduled repeatedly @ the same

Results depending on processing of concurrent events : UNACCEPTABLE

Transport Vs Inertial Delay

Transport Delay The time duration it takes for the effect of gate input changes to appear at gate outputs Inertial Delay The minimum input pulse duration necessary for the output to switch states

Continued

Propagation or Transport delays : Da & Db

Transition or Inertial delay : Dc

Gate Delay Modeling

In modeling the behavior of gate, function and timing are separately

dealt with Activated element is evaluated first Delays are computed later

In high speed circuits, wire delay is comparable to component delay As they depend on wire length, predictable only after routing

Wire Delay

Delay Models
Zero & unit delay models Transition dependent delay models
Delay differs for rise(Dr) & fall(Df) transition
Can result in impossible events

Inverter with Dr = 12 & Df=7 I/P pulse : 1 0 1 of pulse width 4 1st I/P tran schedules O/P @ 12 2nd I/P tran schedules O/P @ 11
Ambiguous delay model
Delay value varies, say Dmin & DMAX

Results in intervals during which the signal

value is not precisely defined

Issues with Arbitrary Delay Model

Computes the earliest & latest times @which signal changes can occur In presence of Reconvergent Fan-out, arbitrary delay model may result

in pessimistic results

Incorrect, because transitions on A & B are dependent Transition on B occurs after *6,10+ only once A is stable No chance of STATIC HAZARD @ C

Other Relevant Terminology (delay)

SETUP / HOLD
Minimum time a signal has

to be present at the input pin of a memory cell before/after the write signal arrives.
RECOVARY / REMOVAL
Minimum time you must

leave between an asynchronous clear/set signal and before/after the clock of the cell is triggered.
MINIMUM PULSE WIDTH
Minimum width a control

signal must have in order for the cell to detect it.

Hazards
Unwanted pulses or glitches ; must analyze dynamic behavior to

detect Static or dynamic

A dynamic hazard refers to the transient pulse during a 0-to- 1 or 1-

to-0 transition

Dynamic 1

Dynamic 0

A static hazard refers to the transient pulse on a signal line whose

static value does not change Static 0

Reference : http://cset.sp.utoledo.edu/eet3350/lesson1.html (look at this link for good treatment of hazards & Avoid them

Static 1

Static Hazard

Dynamic Hazard

Detecting Static Hazards

Directly Extracted from Reference 2 Textbook

Hazard Detection Delay Model Role

I/P Sequence A = 010 Zero Delay Model :
B = 101 & C = 000 ; No Hazard Models only static behavior; Ignores dynamic behavior

Unit Delay Model :

B = 1101 & C = 0010 ; Pulse in response to 0 --> 1 transition of A

Arbitrary Delay Model :

A = 0u1u0 ; B = 1u0u1 ; C = 0u0u0 (from previous slide)
Hazard predicted for both rise & fall transitions of input Overly Pessimistic bcos , in general, one of the paths to AND gate will have

greater delay which will cause a hazard Arbitrary delay model cannot predict which path results in higher delay

Hazard Detection in Async. Ckts

Directly Extracted from Reference 2 Textbook

Example
At time t,
R = S = 0 Q = Qn = 1

At time t+1,
R = S = 1

Step 1 : Set R = S = u => Q = Qn = u Step 2 : Set R = S = 1 => Q = Qn = u Hence, under arbitrary delay model, the operation of the circuit is

unpredictable
Depending on actual delays, the circuit may oscillate

Oscillation Control
Issue : Simulation of a circuit that oscillates results in repeated

scheduling & processing of same sequence of events : results in endless loop Detecting Oscillations during simulation and taking appropriate corrective action Local oscillation control : Identifying conditions causing oscillations in local sub circuits like latches & Flops Global oscillation control : Identifying signals which have unusually high activity

Assignment - 1
Will be uploaded on the course webpage on 3rd Jan 2011 You need to submit your answers on or before 5PM ; 10th Jan 2011 Solutions for all the problems will be uploaded @ 5PM ; 10th Jan

2011 No copying ; 0 marks if find any two solutions following the same pattern No Late Submission ; 0 marks in this case also