Combinational PLDs

Programmable Array Logic (PALs)

• PAL is a PLD with a fixed OR array and a
programmable AND array.
• Since only AND gates are programmable, the PAL is
easier to program and fast but is not flexible as PLA.
• Figure shows the logic configuration of a typical PAL.
(4 I/Ps and 4 O/Ps). Each input has a buffer-inverter gate
and each output is generated by a fixed OR gate.
• There are 4 sections, each being composed of a 3 wide
AND-OR array(meaning 3 programmable AND gates in
each section and one fixed OR gate).
Programmable Array Logic (PALs)
Programmable Array Logic (PALs)

Programmable
AND plane and
fixed OR plane.

PALs have a built-in

circuit to initialize all
registers to zero.
 Programmable Array Logic (PALs)
• A typical PAL IC may have 8 inputs, 8 outputs, and
8 sections, each consisting of an 8-wide AND-OR
array. Output terminals are sometime driven by 3-
state buffers or inverters.
• When designing a PAL, the Boolean function must
be simplified to fit into each section. Unlike the
PLA, a product term cannot be shared among two
or more gates.
• Therefore, each function can be simplified by itself
without regard to common product terms.
Programmable Array Logic (PALs)
Unprogrammed

Programmed
 Using PALs: An Example
x1 x2 x3
Implement the following:
f1 = x1x2 x' 3 + x'1 x' 2 x3
f2 = x'1 x' 2 + x1x2 x3
P1

P2

P3

P4

AND plane
 Using PALs: An Example
x1 x2 x3

f1 = x1x2 x' 3 + x'1 x' 2 x3

f2 = x'1 x' 2 + x1x2 x3
P1

f1
P2

P3

f2
P4

AND plane
 Using PALs
• The number of product terms in each section is
fixed, and if the number of terms in the function is
too large it may be necessary to use two sections
to implement one Boolean function.
• Consider the following example:

w = ABC '+ A' B ' CD '

w( A, B, C , D) = ∑ (2,12,13)
x = A + BCD
x( A, B, C , D) = ∑ (7,8,9,10,11,12,13,14,15)
y = A' B + CD + B ' D'
y ( A, B, C , D) = ∑ (0,2,3,4,5,6,7,8,10,11,15)
z ( A, B, C , D) = ∑ (1,2,8,12,13)
z = ABC '+ A' B ' CD '+ AC ' D'+ A' B ' C ' D
= w + AC ' D'+ A' B ' C ' D
 Using PALs
PAL Programming Table:
Using PALs
 Sequential PLDs
• Digital systems are designed using flip-flops and
gates. Since the combinatorial PLD consists of only
gates, it is necessary to include external flip-flops
when they are used in design.
• Sequential programmable devices include both
gates and flip flops.
• In this way, the device can be programmed to
perform a variety of sequential circuit functions.
• The major types are:
– Sequential programmable logic devices (SPLD)
– Complex Programmable Logic Device (CPLD)
– Field Programmable Gate Array (FPGA)
 Sequential PLDs
• Sequential PLD is sometimes referred to as a simple
PLD to differentiate it from the complex PLD.
• SPLD includes flip-flops within the integrated
circuit chip in addition to the AND-OR array.
• A PAL or PLA is modified by including a number
of flip-flops connected to form a register.
• The circuit output can be taken from the OR gates
or from the outputs of flip-flops.
• Additional programmable connections are available
to include the flip-flops (D or JK type) outputs in
the product terms formed with the AND array.
Sequential PLDs
 Sequential PLDs
• The configuration mostly used for SPLD is the
combinatorial PAL together with D flip-flops.
• A PAL that includes flip-flops is referred to as a
registered PAL.
• Each section of an SPLD is called a macrocell.
• A macrocell is a circuit that contains a sum-of-
products combinational logic function and an
optional flip-flop.
• A typical SPLD has from 8 to 10 macrocells
within one IC package.
 Sequential PLDs
• A typical macrocell can have the following
programming options
– Ability to either use or bypass the flip-flop
– Selection of clock edge polarity
– Selection of preset and clear for the register
– Selection true and complement of an output. An XOR
gate is used to program a true/complement condition.
• Multiplexers are used to select between two or
four distinct paths by programming the selection
inputs.
 PALs
• Classification of PAL Devices
- Combinational PALs
- Sequential PALs
- Arithmetic PALs

Most Popular
Series 20 and series 24 PAL devices
 Combinational PAL devices
• NAND-NAND, OR-NAND, NOR-OR expressions
can be implemented with active high output devices
• NAND-AND, OR-AND and NOR-NOR
expressions can be implemented with active low
output devices

• Number of product terms is limited just like in

PLAs (typically 8)
• Number of inputs to OR gate(fixed) is also limited
(2, 4, 8 or 16)
 Series 20 PALs
• Combinational PAL devices
PAL10H8 PAL10L8 PAL16C1
PAL12H6 PAL12L6
PAL14H4 PAL14L4
PAL16H2 PAL16L2
• General naming convention
PALxYz
x - Number of inputs to AND array (vs dedicated i/ps)
Y - Output type
z - Number of outputs (approx. = No. of Macrocells)
 Series 20 PALs
• Output types (Y)
H - Active high (OR gate)
L - Active Low (NOR gate)
C - true and complement output available

Eg:
PAL16H8
16 inputs to AND array
10 dedicated inputs (+ 6 feedback inputs)
8 outputs
Output is an OR gate (active high)
Number of product term per OR gate is 8 (typical value)
 Increment

Series 20 PALs
1
0 4 8 12 16 20 24 28

0
First 32
fuse 64
numbers 96
128 19
160
192
224
2

256
288

PAL16H8
320
352
384 18
416
448
480

512
544
576
608
640 17
672
704
736
4

768
800
832
864
896 16
928
960
992

1024
1056
1088
1120
1152 15
1184
1216
1248
6

1280
1312
1344
1376
1408 14
1440
1472
1504

1536
1568
1600
1632
1664 13
1696
1728
1760
8

1792
1824
1856
1888
1920 12
1952
1984
2016

9 11

Note: Fuse number = first fuse number + increment

 Series 20 PALs
• Sequential PAL devices

PAL16L8 PAL16A4
PAL16R8 PAL16X4
PAL16R6 PAL16P8
PAL16R4

R - Registered output
P - Programmable I/O
Series 20 PALs: Typical output structures
 Sequential PAL devices

PAL16L8 - No flip flops : but outputs are fed back to

input side
PAL16R4 - 4 registered outputs
4 outputs not registered
8 dedicated inputs
8 feedback inputs
OE, CLK, Vcc, GND
Typically 8 product terms per OR gate
PAL16L8 - Logic Diagram
PAL16L8 - Logic Diagram
Logic Diagram for 16R4 PAL
Logic Diagram for 16R4 PAL
 Arithmetic PAL devices
• Outputs of 2 or more OR gates fed to EX-OR gate
so that arithmetic functions can be easily generated
• PAL16A4 and PAL16X4 devices
1 2 3

P1

P2

P3

P4

Simple ALUs can easily be implemented

 Series 24 PALs
• 24 pin versions of PAL devices
Typically 10 inputs and 10 outputs
PAL12L10 PAL20C1
PAL14L8 PAL20L10
PAL16L6 PAL20X10
PAL18L4 PAL20X8
PAL20L2 PAL20X14

PAL22V10 - most popular among all PAL devices

V - versatile output
 PAL22V10

General features
• 22 inputs and 10 outputs
• All 10 outputs go through OLMC
• 12 dedicated inputs (including a clock)
• 8 to 16 product terms per OR gate
• Typical input to output delay of 5/10 ns
• Reprogrammable version: PALCE22V10
 PAL22V10

Functional Diagram
PAL22V10
PAL22V10
 OLMC of PAL22V10
Output Logic MacroCell (OLMC) is a standard design
used in most of the PLDs

TI Design
 OLMC of PAL22V10
OLMC output options
 OLMC of PAL22V10
OLMC output options
 PAL
• Designing Circuits with PAL devices is also an
automated process (most of the cases)

• One can use VHDL, Verilog, ABEL(advanced Boolean

Expression Language), PALASM or similar language to
do this

• If you don’t like using CAD tools you have the option
of representing your design as a programming table

• But before using a PAL/ and PLD its better to be

familiar with the internal details of the device so that
one can optimally use a PAL ( or any PLD for that
reason)
• Don’t use a PAL to design an f= ax + ax’ !