Data Converter Architectures

Example 29.1
Design a 3-bit resistor string ladder using a binary switch array. Assume that VREF = 5 V and that the maximum power dissipation of the converter is to be 5 mW (not including the power required by the digital logic). Determine the value of the analog voltage for each of the possible digital input codes.

Mismatch Errors Related to the Resistor String DAC

The accuracy of the resistor string is - obviously related - to matching between the resistors, which ultimately determines - the INL and DNL for the entire DAC.

This equation helps us to determine the NonLinearity Errors.

Integral Nonlinearity of the Resistor String DAC

Integral nonlinearity (INL) is defined as the difference between the actual and ideal switching points,

This expression, - requires the mismatch of all the resistances used in the summation to be known. - does not illustrate how to determine the worst-case or maximum INL for a resistor string.

Integral Nonlinearity of the Resistor String DAC

worst-case INL: the maximum INL will occur at 1. the midpoint of the string corresponding to i = 2N- l , (corresponding to the case where the MSB was a one and all other bits were zero). 2. Another condition that will ensure a worst-case scenario will be to consider the lower half resistors - at their maximum positive mismatch value and upper half resistors - at their maximum negative mismatch value, or vice versa.

This expression, - the worst-case INL (again, assuming 2 percent matching). - determine the effective resolution" of a DAC.

Example 29.2
Determine the effective number of bits for a resistor string DAC, which is assumed to be limited by the INL. The resistors are passive poly resistors with a known relative matching of 1 percent and VREF =5 V.

Differential Nonlinearity of the Worst-Case Resistor String DAC

DNL = (the actual height of the stair-step in the DAC transfer curve) - (the ideal step height)

From this expression, - the maximum DNL will occur at the value of i for which ^R is at its maximum value The worst-case DNL (The resistors are matched to within 2 percent)

which is well below the 1/2 LSB limit. NOTE: The INL is obviously the limiting factor - in determining the resolution of a resistor string DAC - since INLs maximum value is 2N times largerthantheDNL.

R-2R Ladder Networks

R-2R Ladder Networks

Each node voltage is related to VREF , byabinary-weightedrelationshipcausedby the voltage division of the ladder network.

ThetotalcurrentflowingfromVREF isConstant,sincethepotentialatthebottomof each switched resistor is always zero volts (either ground or virtual ground).
Therefore,thenodevoltageswillremainConstant- for any value of the digital input. The output voltage, V OUT' is dependent on currents flowing through the feedback resistor, RF , such that

where iTOT is the sum of the currents selected by the digital input by

where Dk, is the k-th bit of the input word with a value that is either a 1 or a O.

R-2R Ladder Networks

This architecture, like the resistor string architecture, - requires matching to within the resolution of the converter. Therefore, theswitchresistancemustbenegligible,(orelsea'smallvoltage drop' will occur across each switch, resulting in an error).

Onewaytoeliminatethisproblemistoadddummyswitches.

R-2R Ladder Networks with Dummy switch

Dummy switches with 1/2 the resistance of the real switches - are "hard-wired" so that they are always ON and placed in series with each of the horizontal resistors. The total resistance of any horizontal branch, R' , is R' = R + ^R/2 The resistance of any vertical branch is 2R + ^R, - which is twice the value of the horizontal branch. Therefore, a R' - 2R' relationship is maintained.

Example 29.3
Design a 3-bit DAC using a R-2R architecture with R =1 k ohm, RF =2 k ohm, and VREF = 5 V. Assume that the resistances of the switches are negligible. Determine the value of iTOT for each digital input and the corresponding output voltage, vOUT'

Example 29.3