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Need for Testing Manufacturing Test Principles Design Strategies for Test Chip Level Test Techniques System Level Test Techniques
Why Testing?
Testing is one of the most expensive parts of chips Logic verification accounts for > 50% of design effort for many chips
Debug time after fabrication has enormous opportunity cost Shipping defective parts can sink a company
By detecting a malfunctioning chip early, the manufacturing cost can be kept low.
Why Testing?
Yield = Number of good die / Total number of die per wafer. Because of the complexity of the manufacturing process, not all die on a wafer function correctly. Dust particles and small imperfections in starting material or photo masking can result in a bridged connections or missing features and these imperfections are called faults. Testing a chip can occur at
Wafer level Packaged chip level Board level System level Field level.
Test Categories
Functionality Tests (Logical Verification)
Silicon Debug Manufacturing Tests
Logical Verification
Usually done at HDL level Verification engineers write test bench for HDL
Cant test all cases Look for corner cases Try to break logic design
Silicon Debug
Run on the first batch of the chips that return from the fabrication.
Much more extensive than the first one because the chip can be tested at a full speed in a system. Required to locate the cause of failures because the designer has less visibility into the fabricated chip compared to during design verification.
Manufacturing Tests
Verify that every transistor, gate and storage element in the chip functions correctly. A speck of dust on a wafer is sufficient to kill chip Yield of any chip is < 100%
Must test chips after manufacturing before delivery to customers to only ship good parts
Manufacturing Tests
Same tests can be used for all three steps It is easier to use one set of tests to chase down the logic bugs and another, separate set optimized for manufacturing defects.
Types of Faults
Fault Any condition that causes a device to function improperly. Solid or Permanent Fault
A faulty condition that does not change with time. A faulty condition that appears and disappears with time. Faults that cause a given logical device to function entirely different logic device. All faults other than logical faults
Intermittent Fault
Logical Faults
A popular and useful model for representing faults in the logic device. Types of model
Stuck-at logic zero (s-a-0) Stuck-at logic one (s-a-1) Gate oxide shorts Metal-to-metal shorts
Short-Circuit Faults
Other Names: Stuck-closed faults or Bridging faults The short S1 results in an SA-0 fault at input A The short S2 modifies the function of the gate. To ensure the most accurate modeling, faults should be modeled at the transistor level because the complete circuit structure is known only at this level.
By observing static current (IDD) while applying test vectors A 2-input NOR gate Fault The drain connection on a pMOS transistor is shorted to VDD. This fault occurs due to the overlapping of stray metal on the VDD line and drain connections. Identifying the faults Apply the test vectors 01 or 10 to the A and B inputs Measure the static IDD Notice that it rises to some value determined by size of the nMOS transistors.
Convert a combinational logic circuit into a sequential logic circuit. A 2-input NOR gate. One of the transistors rendered is ineffective. If the nMOS transistor A is stuck open, then the function displayed by the gate will be
Timing is also included. Still works with increased tpdf. Fault become sequential as the detection of the fault depends on the previous state of the gate. Occurs due to crosstalk. Occurs in SOI due to history effect.
To increase Testability
Increase Observability
Add small probe bus, selectively enable different values onto bus
Use a hash function to compress a sequence of values (e.g., the values of a bus over many clock cycles) into a small number of bits for later read read-out
Cheap read read-out of all state information Use muxes to isolate sub sub-modules and select sources of test data as inputs Provide easy setup of internal state
Increase Controllability
Fault Coverage
What percentage of the chips internal nodes were checked? Should be excess of 98.5% fault coverage. Take each circuit node in sequence. Held to 0 (S-A-0) Identify the faults Held to 1 (S-A-1) Identify the faults
Total nodes detected as faulty Fault Coverage =
Procedure
For given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output. Majority of available tools: combinational networks only Sequential ATPG available from academic research.
Most ATPG approaches have been based on simulation. A five vale logic is used to implement test generation algorithms 1 0 X D Logic One Logic Zero Unknown or Dont Care Condition Logic 1 in good machine. Logic 0 in faulty machine
Generate pseudo-random inputs to combinational logic. Combine outputs into a syndrome. With high probability, block is fault-free if it produces the expected syndrome
Rapidly becoming more important with increasing chip-complexity and larger modules
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