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SAJESH KUMAR U
Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
switches
Memory array
N i/o
lines decoder 2N X m bits
M o/p lines
Q1 Q2 Q3 X Q1+ Q2+ Q3+ Z
0 0 0 0 1 0 0 1
0 0 0 1 1 0 1 0
0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0
. . . . . . . .
. . . . . . . .
. . . . . . . .
REALIZATION OF MEALY
MACHINE
z
x D Q1
Q1+
CK
ROM
Q2
D
16x4 Q2+ CK
Q3+ D Q3
CK
CLK
General structure of a PLA.
x 1 x2 xn
Input buffers
and
inverters
x 1 x1 xn xn
P1
f1 fm
Gate-level diagram of a PLA.
x1 x2 x3
Programmable
connections
OR plane
P1
P2
P3
P4
AND plane
f1 f2
Customary schematic of a PLA
1 2 3
OR plane
P1
P2
P3
P4
AND plane
f1 f2
An example of a PAL
x1 x2 x3
P1
f1
P2
P3
f2
P4
AND plane
Cypress PAL 22V10
Structure of a CPLD
I/O block
I/O block
PAL-like PAL-like
block block
Interconnection wires
I/O block
I/O block
PAL-like PAL-like
block block
A section of a CPLD
PAL-like block
D Q
D Q
D Q
Structure of an FPGA.
I/O block
I/O block
I/O block
A two-input lookup table (LUT).
Inclusion of a flip-flop with a LUT
S e le c t
Out
F lip -flo p
In1
In2 LUT D Q
In3
C lo c k
A section of a programmed FPGA
x3 f
x1
x1 0 x2 0
0 f1 1 f2
0 0
x2 x2 x3
1 0
f1 0
1 f
1
f2
1
FPGA technologies
Antifuse
- One Time Programmable technology (OTP)
SRAM
- Reprogrammable FPGA technology, uses SRAM
configuration cell
Flash
- Reprogrammable and Nonvolatile FPGA
technology
Comparison of FPGA technologies
Feature SRAM Antifuse Flash
Reprogrammable Yes (ISP) No Yes (ISP)
Volatile Yes No No
Programmable
IOBs
Programmabl
e interconnect
Typical Logic Cell (Xilinx)
B
G-LUT
SR
G4 Logic
G4
Function D Q YQ
G3 of G1-G4 G3
G CK
G2 G2
EC
G1 G1 H-LUT
SR G4 Logic Y
Function
H1 H1 of F, G, H
H1
DIN F
F4 Logic SR
F4
Function A D Q XQ
F3 of F1-F4 F3
F CK
F2 F2
EC
F1 F1
F-LUT Y
Multiplexer Controlled
by Configuration Program
K
EC
Simplified IOB (Xilinx)
• Fast I/O drivers
DFF/LATCH
D Q
CE
output,
3-state enable
control D
DFF/LATCH
Q
CE
• Programmable S/R
PAD
• Selectable I/O CE
standards
S/R
FPGA DESIGN FLOW
RTL Design Test Bench
STA
HDL Simulator
Schematic entry
Flow chart
Netlist
Synthesis Example
architecture counter_a of counter is
signal q :std_logic_vector(2 downto 0) ;
library ieee; begin
use ieee.std_logic_1164.all; process(clk,rst)
use ieee.std_logic_unsigned.all; begin
entity counter is if (rst='1')then
Port q<="000";
( elsif (clk'event and clk='1') then
clk : in std_logic ; if (q="100")then q<="000";
rst : in std_logic ; else q<=q+'1';
output : out std_logic_vector(2 downto 0) end if;
); end if;
end counter; end process;
output<=q;
end counter_a;
Synthesiser Output
Floor planning
Netlist Chip
Placement
Chip Block
Routing
Back-annotated Netlist
Post Layout Simulation
Basic VHDL
ENTITY
Code Structure
Architecture
PACKAGE
FUNCTIONS
PROCEDURES
COMPONENTS
CONSTANTS
TYPES
Entity
Entity defines a new component, its IO connections
and related declarations.
_____example________________________________
entity my_and is
port ( a : in std_logic; -- Input Port
b : in std_logic; -- Input Port
c : out std_logic); -- Output Port
end my_and;
Architecture
Architecture specifies the behavior, function, interconnection and the
entity my_and is
port ( a : in std_logic;
b : in std_logic;
c: out std_logic);
end my_and;
begin
u0:AND2 port map (x => a, y => b, z=> c);
end my_and_struct;
___Data flow Style____________________________
entity my_and is
port ( a : in std_logic;
b : in std_logic;
c: out std_logic);
end my_and;
c <= a and b;
end my_and_data;
Configuration
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_1164_unsigned.all ;
library my_library ;
use my_library.my_package.all ;
Package
A package is a collection of commonly used
subprograms, data types and constants.
Package promotes code reuse.
STANDARD and TEXTIO are provided in the STD
library that defines useful data types and utilities.
‘USE’ statement is used to access components
inside a library.
Package (contd..)
Package consists of two parts-
Package Header - defines the contents of a package
that is made visible after the statement.
“use library.package_name.all”.
package my_package is
type state is (st1 st2, st3, st4);
constant vec : std_logic_vector(7 downto 0) := “11110000”;
function positive_edge (signal s: std_logic) return boolean;
end my_package;
signal a : std_logic
Class
• Class types: Constant, Variable, Signal
– Constant
can be declared in all parts of a program
can be of any type
used to make the code more readable
constant a : std_logic_vector :=“1010”
– Variable
• Identifier used in a process or a subprogram for local
data storage
• have only type and value attached, no past history
variable j : integer range 0 to 10;
Class
– Signal
• connects design entities together and communicates
changes in values.
cycle run.
statements.
signal clk : std_logic;
begin
a <= b; b <= c;
______example___________________________
entity my_ex is
port ( a,b,c : in std_logic;
data : in std_logic_vector(1 downto 0);
q : out std_logic);
end my_ex;
architecture my_ex_a of my_ex is
begin
q <= a when data=“00” else
b when data=“11” else
c;
end my_ex_a;
Selective Signal Assignment
_____syntax_________________________________
process (sensitivity list)
declarations;
begin
sequential statements;
end process;
Sequential statement
____________example_______________________
process (a, b, c)
begin
d <= (a and b) or c ;
end process;
Clocked process
_____example____________________________________
process(clk, rst)
begin
if rst = ‘1’ then
q <= ‘0’ elsif( clk’event and clk = ‘1’ then)
q <= d;
end if;
end process;
The if statement
• An if statement selects one or more of a sequence of
events to execute depending on a condition.
• If statement can be nested.
• If statement generates a priority structure.
• If corresponds to when statement in the concurrent
part.
____example____________________
component AND2
port ( x: in std_logic;
y: in std_logic;
z: out std_logic);
end component;
begin
u0:AND2 port map (x => a, y => b, z=> c);
end my_and_struct;
Delays in VHDL