CS1104 Computer Organization

http://www.comp.nus.edu.sg/~cs1104

Aaron Tan Tuc Cho! Schoo" o# Computing $ationa" %ni&ersit! o# Singapore

'ecture 11: Se(uentia" 'ogic 'atches ) *"ip+#"ops

Introduction Me or! "le ents #ulse-$riggered Latch
S-% Latch &ated S-% Latch &ated ' Latch

"dge-$riggered Flip-flops

S-% Flip-flop ' Flip-flop (-) Flip-flop $ Flip-flop

*s!nchronous Inputs
CS1104-11 Lecture 11: Sequential Logic: Latches & Flip-flops 2

,ntroduction
* sequential circuit consists of a feedback path,
and e plo!s so e memory elementsCo .inational outputs Me or! outputs

Co .inational logic

Me or! ele ents

"/ternal inputs

Sequential circuit 0 Co .inational logic 1 Me or! "le ents

CS1104-11 Introduction +

,ntroduction
$here are t2o t!pes of sequential circuits:
synchronous: outputs change onl! at specific ti e asynchronous: outputs change at an! ti e

Multivibrator: a class of sequential circuits- $he!

can .e:
bistable 32 sta.le states4 monostable or one-shot 31 sta.le state4 astable 3no sta.le state4

5ista.le logic de6ices: latches and flip-flops Latches and flip-flops differ in the ethod used for
changing their stateCS1104-11 Introduction 4

-emor! ."ements
Memory element: a de6ice 2hich can re e .er
6alue indefinitel!, or change 6alue on co fro its inputsco and Me or! ele ent Q

and

stored 6alue

Characteristic ta.le:
Co and 3at ti e t4 Set %eset Me orise 9 :o Change
CS1104-11

Q(t) 8 8 0 1

Q(t+1) 1 0 0 1

Q(t): current state Q(t+1) or Q+: ne/t state

Me or! "le ents

-emor! ."ements
Me or! ele ent 2ith cloc<- Flip-flops are e or!
ele ents that change state on cloc< signalsco and Me or! ele ent Q stored 6alue

cloc<

Cloc< is usuall! a square 2a6e#ositi6e pulses

#ositi6e edges
CS1104-11

:egati6e edges
Me or! "le ents ;

-emor! ."ements
$2o t!pes of triggering9acti6ation:
pulse-triggered edge-triggered

#ulse-triggered
latches >: 0 1, >FF 0 0

"dge-triggered
flip-flops positi6e edge-triggered 3>: 0 fro

0 to 1? >FF 0 other 1 to 0? >FF 0 other

ti e4 negati6e edge-triggered 3>: 0 fro ti e4

CS1104-11 Me or! "le ents

S+/ 'atch
Complementary outputs: Q and Q' Ahen Q is BI&B, the latch is in S ! state Ahen Q is L>A, the latch is in " S ! state For active-#$%# input S-% latch 3also <no2n as :>%
gate latch4, "0BI&B 3and S0L>A4 %"S"$ state S0BI&B 3and "0L>A4 S"$ state .oth inputs L>A no change .oth inputs BI&B Q and Q' .oth L>A 3in6alid4C

CS1104-11

S-% Latch

S+/ 'atch
For active-&'( input SE-%E latch 3also <no2n as :*:'
gate latch4, "'0L>A 3and S'0BI&B4 %"S"$ state S'0L>A 3and "'0BI&B4 S"$ state .oth inputs BI&B no change .oth inputs L>A Q and Q' .oth BI&B 3in6alid4C

'ra2.ac< of S-% latch: in6alid condition e/ists and

ust .e a6oided-

CS1104-11

S-% Latch

S+/ 'atch
Characteristics ta.le for acti6e-high input S-% latch:
S 0 1 0 1 R 0 0 1 1 Q NC 1 0 0 Q' NC 0 1 0 No change. Latch remained in present state. Latch SET. Latch RESET. In alid condition.
S R Q Q'

Characteristics ta.le for acti6e-lo2 input SE-%E latch:

S' 1 0 1 0 R' 1 1 0 0 Q NC 1 0 1 Q' NC 0 1 1 No change. Latch remained in present state. Latch SET. Latch RESET. In alid condition.
S R Q Q'

CS1104-11

S-% Latch

10

S+/ 'atch
*cti6e-BI&B input S-% latch
10 100 " Q 11000 Q' 0 0 1 1 0
S 1 0 0 0 1 " 0 0 1 0 1 Q Q' 1 0 initial 1 0 3afer S01, "004 0 1 0 1 3after S00, "014 0 0 in6alidC

10 001 S

*cti6e-L>A input SF-%F latch

S' R' Q Q'

S'

Q Q'
S-% Latch

"'
CS1104-11

S' "' 1 0 1 1 0 1 1 1 0 0

Q Q' 0 1 initial 0 1 3afer S'01, "'004 1 0 1 0 3after S'00, "'014 1 1 in6alidC

11

0ated S+/ 'atch

S-% latch 1 enable input 3 )4 and 2 :*:' gates
*ated S-" latchS ) Q' "

S EN R

Q Q'

CS1104-11

&ated S-% Latch

12

0ated S+/ 'atch

>utputs change 3if necessar!4 onl! 2hen ) is
BI&B-

Gnder 2hat condition does the in6alid state occurH Characteristic ta.le:
EN!1
Q(t) 0 0 0 0 1 1 1 1 S 0 0 1 1 0 0 1 1 R 0 1 0 1 0 1 0 1 Q(t+1) 0 0 1 indeterminate 1 0 1 indeterminate

S R 0 0 1 1 0 1 0 1

Q(t+1) No change Q(t) 0 Reset 1 Set indeterminate

Q(t+1) 0 S 1 "'+Q S+" 0 0

1+

CS1104-11

&ated S-% Latch

0ated 1 'atch
Ma<e " input equal to S' *ated , latch+ , latch eli inates the undesira.le condition of in6alid
state in the S-" latch, ) Q'

D EN

Q Q'

CS1104-11

&ated ' Latch

14

0ated 1 'atch
Ahen ) is BI&B,
,0BI&B latch is S"$ ,0L>A latch is %"S"$

Bence 2hen ) is BI&B, Q Ifollo2sF the , 3data4

input-

Characteristic ta.le:
EN 1 1 0 D 0 1 " Q(t+1) 0 1 Q(t) Reset Set No change

Ahen )01- Q(t+1) 0 ,

CS1104-11

&ated ' Latch

17

'atch Circuits: $ot Suita2"e

Latch circuits are not suita.le in s!nchronous logic
circuits-

Ahen the ena.le signal is acti6e, the e/citation

inputs are gated directl! to the output J- $hus, an! change in the e/citation input i ediatel! causes a change in the latch outputcontrol signal called a clock to restrict the ti es at 2hich the states of the e or! ele ents a! changeele ents called flip-flops-

$he pro.le is sol6ed .! using a special ti ing

$his leads us to the edge-triggered e or!

CS1104-11 &ated ' Latch 1;

.dge+Triggered *"ip+#"ops
.lip-flops: s!nchronous .ista.le de6ices >utput changes state at a specified point on a
triggering input called the clock-

Change state either at the positive ed*e 3rising edge4

or at the ne*ative ed*e 3fallin* ed*e4 of the cloc< signalCloc< signal
#ositi6e edges :egati6e edges

CS1104-11

"dge-$riggered Flip-flops

1=

.dge+Triggered *"ip+#"ops
S-%, ' and (-) edge-triggered flip-flops- :ote the KLM
s! .ol at the cloc< inputS C R Q' Q D C Q' Q J C K Q' Q

#ositi6e edge-triggered flip-flops

S C R Q' D C Q' J C K Q'

:egati6e edge-triggered flip-flops

CS1104-11 "dge-$riggered Flip-flops 1@

S+/ *"ip+#"op
S-% flip-flop: on the triggering edge of the cloc< pulse,

S0BI&B 3and "0L>A4 S"$ state "0BI&B 3and S0L>A4 %"S"$ state .oth inputs L>A no change .oth inputs BI&B in6alid

Characteristic ta.le of positi6e edge-triggered S-% flipflop:

S 0 0 1 1 R 0 1 0 1 CLK " Q(t+1) Q(t) 0 1 Comments No change Reset Set In alid

" ! irrele ant #$don%t care&' ! cloc( transition L)* to +I,+ CS1104-11 S% Flip-flop 1D

S+/ *"ip+#"op
It co prises + parts:
a .asic )/), latch a pulse-steerin* circuit a pulse transition detector 3or ed*e detector4 circuit

$he pulse transition detector detects a rising 3or

falling4 edge and produces a 6er! short-duration spike-

CS1104-11

S% Flip-flop

20

S+/ *"ip+#"op
$he pulse transition detectorS CLK .ulse transition detector R Q

Q'

CLK' CLK CLK* CLK CLK' CLK* CLK

CLK' CLK* CLK CLK' CLK*

#ositi6e-going transition 3rising edge4

CS1104-11

:egati6e-going transition 3falling edge4

S% Flip-flop 21

1 *"ip+#"op
' flip-flop: single input , 3data4
,0BI&B S"$ state ,0L>A %"S"$ state

Q follo2s , at the cloc< edge Con6ert S-% flip-flop into a ' flip-flop: add an in6erterD CLK S C R Q' Q
D 1 0 CLK Q(t+1) 1 0 Comments Set Reset

! cloc( transition L)* to +I,+

* positi6e edge-triggered ' flipflop for ed 2ith an S-% flip-flopCS1104-11 ' Flip-flop 22

1 *"ip+#"op
*pplication: 0arallel data transfer$o transfer logic-circuit outputs 1, 2, 3 to flip-flops Q1, Q4 and Q5 for storageD CLK X Q Q' Q Q' Q Q' Q3 ! Z* Q2 ! Y* Q1 ! X*

Com3inational logic circuit

Y Z

D CLK

D Transfer CLK

/ 01ter occurrence o1 negati e2going transition CS1104-11 ' Flip-flop 2+

3+4 *"ip+#"op
(-) flip-flop: J and JE are fed .ac< to the pulsesteering :*:' gates-

:o in6alid state Include a to**le state 60BI&B 3and 70L>A4 S"$ state 70BI&B 3and 60L>A4 %"S"$ state .oth inputs L>A no change .oth inputs BI&B toggle

CS1104-11

(-) Flip-Ffop

24

3+4 *"ip+#"op
(-) flip-flopJ CLK K .ulse transition detector Q

Q'

Characteristic ta.leJ 0 0 1 1 K 0 1 0 1 CLK Q(t+1) Q(t) 0 1 Q(t)' Comments No change Reset Set Toggle

Q 0 0 0 0 1 1 1 1

J K 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

Q(t+1) 0 0 1 1 1 0 1 0 27

Q(t+1) 0 6+Q' 1 7'+Q

CS1104-11 (-) Flip-flop

T *"ip+#"op
$ flip-flop: single-input 6ersion of the (-) flip flop,
for ed .! t!ing .oth inputs togetherT CLK .ulse transition detector Q

T CLK

J C K

Q Q'

Q'

Characteristic ta.leT 0 1 CLK Q(t+1) Q(t) Q(t)' Comments No change Toggle

Q T 0 0 1 1 0 1 0 1 Q(t+1) 0 1 1 0

Q(t+1) 0 !+Q' 1 !'+Q

CS1104-11 $ Flip-flop

2;

T *"ip+#"op
*pplication: .re8uency division+igh J CLK C K CLK Q CLK QA Q Q CLK +igh J C K QA +igh J C K Q

4i ide cloc( 1requency 3y 5.

4i ide cloc( 1requency 3y 6.

*pplication: Counter 3to .e co6ered in Lecture 1+-4

CS1104-11 $ Flip-flop 2=

As!nchronous ,nputs
S-%, ' and (-) inputs are s!nchronous inputs, as
data on these inputs are transferred to the flip-flopFs output onl! on the triggered edge of the cloc< pulseindependent of the cloc<? e/a ple: preset 30" 4 and clear 3C&"4 Nor direct set 3S,4 and direct reset 3",4O

*s!nchronous inputs affect the state of the flip-flop

Ahen 0" 0BI&B, Q is i ediatel! set to BI&B Ahen C&"0BI&B, Q is i ediatel! cleared to L>A Flip-flop in nor al operation ode 2hen .oth 0"
and C&" are L>A-

CS1104-11

*s!nchronous Inputs

2@

As!nchronous ,nputs
* (-) flip-flop 2ith acti6e-L>A preset and clear inputs!RE !RE J Q .ulse transition detector Q'

J C K
CLR CLK !RE CLR

Q
CLK

Q'

K CLR

6 0 7 0 BI&B
CS1104-11

.reset *s!nchronous Inputs

Toggle

Clear 2D

End o1 segment