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2/21/2014
Abhishek KumarSrivastava
2/21/2014
Abhishek KumarSrivastava
Addressing Modes
C5X processors can address 64K words of program memory and 96K words of data memory. C5X supports following 6 addressing modes: 1. Direct addressing 2. Memory-mapped register addressing 3. Indirect addressing 4. Immediate addressing 5. Dedicated-register addressing 6. Circular addressing
2/21/2014
Abhishek KumarSrivastava
2/21/2014
Abhishek KumarSrivastava
Indirect Addressing
Uses Eight 16-bit auxiliary registers (AR0AR7). In indirect addressing, any location in the 64K-word data memory space can be accessed using a 16-bit address contained in an AR. To select a specific AR, load the ARP with a value from 0 through 7, designating AR0 through AR7, respectively. The register pointed to by the ARP is referred to as the current auxiliary register (current AR). You can load the address into the AR using the LAR instruction.
2/21/2014
Abhishek KumarSrivastava
2/21/2014
Abhishek KumarSrivastava
You can change the content of the AR by the: ADRK instruction (The 8-bit immediate value, right-justified, is added to current AR using ARAU. The result is stored in the AR.) MAR instruction (The MAR instruction modifies the ARs or the ARP bits, and the old ARP bits are copied to the ARB bits.) SBRK instruction (The 8-bit immediate value, right-justified, is subtracted from the current AR using ARAU. The result is stored in the current AR.)
2/21/2014
Abhishek KumarSrivastava
The content of the current AR is used as the address of the data memory operand. After the instruction uses the data value, the content of the current AR can be incremented or decremented by the auxiliary register arithmetic unit (ARAU), which implements unsigned 16-bit arithmetic. The ARAU performs auxiliary register arithmetic operations in the decode phase of the pipeline. This allows the address to be generated before the decode phase of the next instruction.
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The content of the current AR is incremented or decremented after it is used in the current instruction. You can load the ARs via the data bus by using memorymapped writes to the ARs. Be careful when using these memory-mapped loads of the ARs because, in this case, the memory-mapped ARs are modified in the execute phase of the pipeline, causing a pipeline conflict, if one of the next two instruction words modifies same AR (without memory mapped).
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There are two ways to use the ARs for purposes other than referencing data memory addresses: 1. Use the ARs to support conditional branches, calls, and returns by using the CMPR instruction. This instruction compares the content of the current AR with the content of the auxiliary register compare register (ARCR) and puts the result in the test/control (TC) flag bit of status register ST1. 2. Use the ARs for temporary storage by using the LAR instruction to load a value into the AR and the SAR instruction to store the AR value to a data memory location.
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Bit-Reversed Addressing
In the bit-reversed addressing mode, INDX specifies one-half the size of the FFT. The value contained in the current AR must be equal to 2n-1, where n is an integer, and the FFT size is 2n. An auxiliary register points to the physical location of a data value. When you add INDX to the current AR using bit-reversed addressing, addresses are generated in a bit-reversed fashion. When you add INDX to the current AR using bit-reversed addressing, addresses are generated in a bit-reversed fashion. Assume that the auxiliary registers are eight bits long, AR2 represents the base address of the data in memory (0110 00002), and that INDX contains the value 0000 10002.
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Immediate Addressing
In immediate addressing, the instruction word(s) contains the value of the immediate operand. The C5x has both 1-word (8-bit, 9-bit, and 13-bit constant) short immediate instructions and 2-word (16-bit constant) long immediate instructions.
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Dedicated-Register Addressing
The dedicated-registered addressing mode operates like the long immediate addressing mode, except that the address comes from one of two special-purpose memory-mapped registers in the CPU: the block move address register (BMAR) and the dynamic bit manipulation register (DBMR). The advantage of this addressing mode is that the address of the block of memory to be acted upon can be changed during execution of the program.
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The PLU executes a read-modify-write operation on data stored in data space. First, one operand is fetched from data memory space, and the second is fetched from a long immediate on the program bus or from the dynamic bit manipulation register (DBMR). Then, the PLU executes a logical operation on the two operands as defined by the instruction. The result is written to the same data memory location from which the first operand was fetched, without affecting ACC or PREG.
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Role of PFC
A 16-bit counter used to prefetch program instructions. The PFC contains the address of the instruction currently being prefetched and is updated when a new prefetch is initiated. Once an instruction is prefetched, the instruction is loaded into the IREG, unless the IREG still contains an instruction currently executing, in which case the prefetched instruction is stored in the QIR (Queue Instruction Register). The PFC is then incremented, and after the current instruction has completed execution, the instruction in the QIR is loaded into the IREG to be executed. The PFC is also used to address program memory when using the block move (BLPD), multiply-accumulate (MAC/MACD), and table read/write (TBLR/TBLW) instructions and to address data memory when using the block move (BLDD) instruction.
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Role of PFC
The long immediate addressing or BMAR also could apply for a second data memory access for the execution of the instruction (Immediate Addressing Mode). The prefetch counter (PFC) is pushed onto the microcall stack (MCS), and the long immediate value or BMAR is loaded into the PFC. The program address/data bus is then used for the operand fetch or write. At the completion of the instruction, the MCS is popped back to the PFC, the program counter (PC) is incremented by two (long immediate operand), and execution continues.
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Using these instructions does not affect the contents of the DP: LAMM Load accumulator with memory-mapped register LMMR Load memory-mapped register with the contents of the data memory location addressed by the 16-bit source address, #addr. SAMM Store accumulator in memory-mapped register SMMR Store memory-mapped register with the contents of the data memory location addressed by the 16-bit source address, #addr.
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Circular Addressing
The C5x supports two concurrent circular buffers (for algorithms such as convolution, correlation, and FIR filters) operating via the ARs. The following five memory-mapped registers control the circular buffer operation: 1. CBSR1 Circular buffer 1 start register 2. CBSR2 Circular buffer 2 start register 3. CBER1 Circular buffer 1 end register 4. CBER2 Circular buffer 2 end register 5. CBCR Circular buffer control register
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The 8-bit CBCR enables and disables the circular buffer operation. To define circular buffers, we first load the start and end addresses into the corresponding buffer registers; next, load a value between the start and end registers for the circular buffer into an AR. Load the proper AR value, and set the corresponding circular buffer enable bit in the CBCR. If (ARn = CBER) and (any AR modification), Then: ARn = CBSR. Else: ARn = ARn + step. Circular buffers can be used in increment- or decrement-type updates.
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Load AR
Load ACC with content available at address held in AR6
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