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Topics

Design rules and fabrication. SCMOS scalable design rules.

Modern VLSI Design 3e: Chapter 2

Copyright 1998, 2002 Prentice Hall PTR

Why we need design rules


Masks are tooling for manufacturing. Manufacturing processes have inherent limitations in accuracy. Design rules specify geometry of masks which will provide reasonable yields. Design rules are determined by experience.

Modern VLSI Design 3e: Chapter 2

Copyright 1998, 2002 Prentice Hall PTR

Manufacturing problems
Photoresist shrinkage, tearing. Variations in material deposition. Variations in temperature. Variations in oxide thickness. Impurities. Variations between lots. Variations across a wafer.

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Transistor problems

Variations in threshold voltage:


oxide thickness; ion implantation; poly variations.

Changes in source/drain diffusion overlap. Variations in substrate.

Modern VLSI Design 3e: Chapter 2

Copyright 1998, 2002 Prentice Hall PTR

Wiring problems
Diffusion: changes in doping -> variations in resistance, capacitance. Poly, metal: variations in height, width -> variations in resistance, capacitance. Shorts and opens:

Modern VLSI Design 3e: Chapter 2

Copyright 1998, 2002 Prentice Hall PTR

Oxide problems
Variations in height. Lack of planarity -> step coverage.
metal 2 metal 2 metal 1

Modern VLSI Design 3e: Chapter 2

Copyright 1998, 2002 Prentice Hall PTR

Via problems
Via may not be cut all the way through. Undersize via has too much resistance. Via may be too large and create short.

Modern VLSI Design 3e: Chapter 2

Copyright 1998, 2002 Prentice Hall PTR

MOSIS SCMOS design rules


Designed to scale across a wide range of technologies. Designed to support multiple vendors. Designed for educational use. Fairly conservative. http://www.mosis.com/design/rules/
The standard CMOS technology accessed by MOSIS is a single polysilicon, double metal, bulk CMOS process with enhancement-mode n-MOSFET and p-MOSFET devices.
Copyright 1998, 2002 Prentice Hall PTR

Modern VLSI Design 3e: Chapter 2

and design rules


is the size of a minimum feature. Specifying particularizes the scalable rules. Parasitics are generally not specified in units

Modern VLSI Design 3e: Chapter 2

Copyright 1998, 2002 Prentice Hall PTR

Wires
All wire widths are multiples of
6 metal 3

3
3

metal 2
metal 1

3
2
Modern VLSI Design 3e: Chapter 2

pdiff/ndiff
poly
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Transistors
poly 3 2 2 3 1

diffusion
substrate

All measures are multiples of


Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Vias

Types of via: metal1/diff, metal1/poly, metal1/metal2.


4 1
2 4

Modern VLSI Design 3e: Chapter 2

Copyright 1998, 2002 Prentice Hall PTR

Metal 3 via
Type: metal3/metal2. Rules:

cut: 3 x 3 overlap by metal2: 1 minimum spacing: 3 minimum spacing to via1: 2

Modern VLSI Design 3e: Chapter 2

Copyright 1998, 2002 Prentice Hall PTR

Tub tie

4 1

Modern VLSI Design 3e: Chapter 2

Copyright 1998, 2002 Prentice Hall PTR

Spacing
diffusion/diffusion: 3 poly/poly: 2 poly/diffusion: 1 via/via: 2 metal1/metal1: 3 metal2/metal2: 4 metal3/metal3: 4

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Overglass
Cut in passivation layer. Minimum bonding pad: 100 m. Pad overlap of glass opening: 6 Minimum pad spacing to unrelated metal2 or metal3: 30 Minimum pad spacing to unrelated metal1, poly, active: 15

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR

Layout design and analysis tools


Layout editors are interactive tools. Design rule checkers are generally batch--identify DRC errors on the layout. Circuit extractors extract the netlist from the layout. Connectivity verification systems (CVS) compare extracted and original netlists.

Modern VLSI Design 3e: Chapter 2 Copyright 1998, 2002 Prentice Hall PTR