UNIT II

Structural Units of Processor Memory Allocation, Memory Map Memory Blocks of System Serial Communication using I2C,CAN and Adv. I/O buses Device Drivers, Virtual Devices ,drivers for parallel , serial ports & timing devices Context Switching, Deadline and Interrupt Latency

Structural Units of Processor

Memory Address Register(MAR):
It holds address of byte or word to be fetched from external memory. Processor issues value to MAR before fetch cycle.

Memory Data Register(MDR):

Holds byte or word fetched from external memory or I/O address.

Internal Bus:
It internally connects all the structural units inside processor. Its width can be of 8, 16, 32, or 64bits.

Address Bus:
External Bus that carries the address from MAR to the memory as well as to I/O devices and other units of system.

 Data Bus:
External Bus that carries bytes of instruction or data during read or write operation.

Control Bus:
External bus that carries control signals to or between processor and memory.

Bus Interface unit:

Interface between processors internal units with external buses.

Instruction Register:
It takes sequentially instruction codes(obcodes) to execution unit of processor.

 Instruction Decoder:
It decodes opcodes received at IR and passes it to Processor CU.

Control Unit:
It controls all bus activities and unit functions needed for processing.

ALU:
To execute arithmetic and logic instructions.

Program Counter:
It generates instruction cycle to fetch address from memory through MAR. Auto increments.

Advance Processing Units:

Units used for multi stage pipeline processing, multi line super scalar processing to obtain speed more than one instruction per cycle.

Advance Processing Units

Includes instruction pipelining units which improves performance by processing instructions in multiple stages.

Superscalar execution unit which improves performance on execution of two or more instructions in parallel.

 Prefetching Unit improves performance by instructions and data in advance for processing.

fetching

Cache and MMU unit improves performance by giving fast instruction and data to processor execution unit. RISC architecture does this by executing instn in single clock cycle, using multiple register set, windows & files and by greatly reducing dependency on external memory access for data due to reduced no. of add modes.
MAC unit at DSP provides fast multiplication of two operands and accumulating results at single address.

Branch Penalty and Data Dependency

If branching instruction is encountered in multi stage pipelining, then the instruction executed in part at the preceding stages becomes redundant. These instructions have to be executed in full again later on after completion of loop or return from routine. In Superscalar unit if there exists two instructions in which one instruction depends on data output of another instruction. Hence these instructions are not aligned properly and cant be placed in separate lines therefore one have to wait and this time is called data dependency penalty.

Allocation of Memory to program segments and blocks

Functions, Processes, Data and stacks at various segments of memory Program routine and processes can have different segments. For e.g. program code can be segmented and each segment stored at different memory block.

Memory Blocks for elements of different Data Structures and Data sets
Stack - is allotted memory block from which data element is always read in LIFO way by processor. - Each processor has at least one stack pointer so that instruction stack can be pointed & calling of routines can be facilited.

Array-important programming element. -M[0],M[1]..M[29] for 1 to 30 resp.

Queue-FIFO data .
Using queues data can be send to network or to printer. two pointers are needed front (data is deleted) and back pointer(data is inserted).

 Circular Queue- Queue is circular queue when pointer reaching on limit, returns to staring address.

List- data structure with number of memory blocks one for each element and each element also storing pointer to next element.

Memory Map
Map to show the program and data allocation of addresses to actual memory
Princeton Architecture: Vectors,pointers,variables,program segments and memory blocks for data and stacks have different addresses in program.eg.8086 [Same memory for data and code]. Harvard Architecture: Processor having this architecture has distinct address spaces, control signals, processor instructions and data paths for bytes of data and for program.[different memory for data and code].

Princeton vs. Harvard architecture

Examples of Memory Map

Example in smart card

Serial Communication using I2C,CAN & Adv I/O buses between networked multiple devices

I2C bus(Inter Integrated circuit)

CAN bus (Controller Area Network) USB bus (Universal Serial Bus)

I2C Bus
Serial bus for connecting ICs Has become a Std bus when multiple ICs need to be integrated. Two lines that carry its signals one for clock and one for BiDirectional Data.

I2C Bus(contd.)
Field Length Explanation

First
Second

1-bit 7-bits 1-bit 1-bit

Start bit Address of slave Sent by master Read or Write cycle in progress Whether present data is acknowledged IC device Data byte NACK(-ve acknowlegde) Stop bit

Third
Fourth

Fifth Sixth
Seventh

8-bits 1-bit 1-bit

Disadvantage of I2C Bus

Time taken by algorithm in the hardware that analyzes the bits through I2C in case the slave hardware does not provide for the hardware that supports it. Certain ICs support the protocol and certain do not. Open collector drivers at the master need a pull-up resistance of 2.2 K on each line.

CAN Bus
Networked devices are controlled by CAN bus. CAN bus is a std bus in distributed network, mainly used in automotive electronics. It has serial line, which is bidirectional.

It receives or sends a bit at instance by operating at maximum rate of 1 Mbps

Node sends or receive data bits as a data frame.

Data frame syntax

Field
First
Second

Length
12-bits 6-bits 0 to 64 bits 16-bits 2-bits

Explanation
Arbitration field
[11bit packet destination address and 1 RTR]

Control Field
[1st identifier,2nd always 1 Rest 4 are code for data length]

Third
Fourth

Length depends on control field (code for data length) CRC word, Receiver uses it to detect error if any.
ACK slot.1st bit depends on acknowledgement of receiver 0(if error) 2nd bit denotes fixed time limit up to which ack should be received.

Fifth

Sixth

7-bits

End of frame, seven zeros

USB
Serial transmission and reception between host and serial devices. Bus between host and no of interconnected peripherals. Provides fast (12Mbps) and low (1.5Mpbs) serial communication and reception between host and serial devices. Two std USB1.1(1.5 to 12Mbps) and USB2.0(480Mpbs).

USB Host Applications

Connecting flash memory cards,

pen-like memory devices,

digital camera,

printer,
mouse-device, Pocket PC, Scanner

 Maximum 127 devices can be connected to a single host. The data transfer is of four types: (a) Controlled data transfer, (b) Bulk data transfer, (c) Interrupt driven data transfer, (d) Iso-synchronous transfer A device can be either bus-powered or self- powered.

USB bus cable has four wires, one for +5V, two for twisted pairs and one for ground.

Features
Can be hot plugged (attached), configured and used, reset, reconfigured and used. Bandwidth sharing with other devices: Host schedules the sharing of bandwidth among the attached devices at an instance. Can be detached (while others are in operation) and reattached.

Attaching and detaching USB device or host without rebooting

Parallel port drivers in System

Device driver read() function can be implemented by calling ISR is Port_ISR_Input, which handle the port input.
Fig (a) shows Control and status bits used in ISR Fig(b) shows Shows step A for Initialization B for device driver 0 to 5 for driver Port _ISR_Input

Port_ISR_Input does the following Step A sets control bits for read, B no action till input event. Steps 0 to 2 for reading the input buffers by emptying the buffer and storing bytes in memory. Step 3 resets device receive-buffer ready flag in status register and prepares device for next read. Step 4 interrupt flag resets to enable next byte read on next interrupt.

Serial port drivers in System

A UART (Universal Asynchronous Receiver/Transmitter) is the microchip with programming that controls a computer's interface to its attached serial devices.

Device drivers for timing devices

Timer device driver programming needs an understanding of programming of each bit of timer control register and status register Programmer must also take into account
Instead of interrupt enable, device may have a mask bit. Also remember that some interrupts are non mask able.

Step I : write in the register that holds timer reset value, no. of count inputs numTicks for RTC Step II: write in status register timer status flag=reset Step III: write each bit present in control register