Tasks and Functions

A designer is frequently required to implement the same functionality at many places in a behavioral design. This means that the commonly used parts should be abstracted into routines and the routines must be invoked instead of repeating the code. Verilog provides tasks and functions to break up large behavioral designs into smaller pieces.
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Differences between...
Functions
Can enable (call) just another function (not task) Execute in 0 simulation time No timing control statements allowed At least one input
Return only a single value
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Tasks
Can enable other tasks and functions May execute in non-zero simulation time May contain any timing control statements May have arbitrary input, output, or inout Do not return any value
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 Both
are defined in a module are local to the module
can have local variables (registers, but not nets) and events contain only behavioral statements do not contain initial or always statements are called from initial or always statements or other tasks or functions

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 Tasks can be used for common Verilog code Tasks are capable of enabling a function as well as enabling other versions of a Task Function are used when the common code
is purely combinational executes in 0 simulation time provides exactly one output

Functions are typically used for conversions and commonly used calculations
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Tasks
Keywords: task, endtask
Must be used if the procedure has
any timing control constructs zero or more than one output arguments no input arguments

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 Task declaration and invocation

Declaration syntax
task <task_name>; <I/O declarations> <variable and event declarations> begin // if more than one statement needed <statement(s)> end // if begin used! endtask

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 Task declaration and invocation

Task invocation syntax
<task_name>; <task_name> (<arguments>);

input and inout arguments are passed into the task output and inout arguments are passed back to the invoking statement when task is completed
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 I/O declaration in modules vs. tasks

Both used keywords: input, output, inout
In modules, represent ports
connect to external signals

In tasks, represent arguments

pass values to and from the task

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Task Example Use of input and output arguments

module operation; parameter delay = 10; reg [15:0] A, B; reg [15:0] AB_AND, AB_OR, AB_XOR;
initial $monitor( ); initial begin end always @(A or B) begin bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B); end
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task bitwise_oper; output [15:0] ab_and, ab_or, ab_xor; input [15:0] a, b; begin #delay ab_and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask

endmodule

Task Example Use of module local variables

module sequence; reg clock;
initial begin end initial init_sequence; always asymmetric_sequence; task init_sequence; clock = 1'b0; endtask task asymmetric_sequence; begin #12 clock = 1'b0; #5 clock = 1'b1; #3 clock = 1'b0; #10 clock = 1'b1; end endtask endmodule
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module traffic_lights; reg clock, red, amber, green; parameter on = 1, off = 0, red_tics = 350, amber_tics = 30, green_tics = 200; initial red = off; initial amber = off; initial green = off;

task light; output color; input [31:0] tics; always begin // sequence to control the lights. begin red = on; // turn red light on repeat (tics) @ (posedge clock); light(red, red_tics); // and wait. color = off; // turn light off. green = on; // turn green light on end light(green, green_tics); // and wait. endtask amber = on; // turn amber light on
light(amber, amber_tics); // and wait. end // task to wait for tics positive edge clocks // before turning color light off.

always begin // waveform for the clock. #100 clock = 0; #100 clock = 1; end endmodule // traffic_lights.
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Automatic (Re-entrant) Tasks:

Tasks are normally static in nature. All declared items are statically allocated and they are shared across all uses of the task executing concurrently. Therefore, if a task is called concurrently from two places in the code, these task calls will operate on the same task variables. It is highly likely that the results of such an operation will be incorrect. To avoid this problem, a keyword automatic is added in front of the task keyword to make the tasks re-entrant. Such tasks are called automatic tasks.

syntax

task automatic<task_name>; <I/O declarations> <variable and event declarations> begin // if more than one statement needed <statement(s)> end // if begin used! endtask
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module top; reg [15:0] cd_xor, ef_xor; reg [15:0] c, d, e, f;

task automatic bitwise_xor; output [15:0] ab_xor; input [15:0] a, b; begin #delay ab_and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask /*These two always blocks will call the bitwise_xor task concurrently at each positive edge of clk. However, since the task is re-entrant, these concurrent calls will work correctly. */ always @(posedge clk) bitwise_xor(ef_xor, e, f); always @(posedge clk2) // twice the frequency as the previous block bitwise_xor(cd_xor, c, d); endmodule 2014 Tasks and Functions

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Functions
Keyword: function, endfunction

Can be used if the procedure

does not have any timing control constructs returns exactly a single value has at least one input argument no output or inout argument no nonblocking assignments

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 Function Declaration and Invocation

Declaration syntax:
function <range_or_type> <func_name>; <input declaration(s)> <variable_declaration(s)> begin // if more than one statement needed <statements> end // if begin used endfunction
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 Function Declaration and Invocation

Invocation syntax:
<func_name> (<argument(s)>);

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 Semantics
much like function in Pascal An internal implicit reg is declared inside the function with the same name The return value is specified by setting that implicit reg <range_or_type> defines width and type of the implicit reg
<type> can be integer or real default bit width is 1
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module function_calling(a, b,c); input a, b ; output c; wire c; function myfunction; input a, b; begin myfunction = (a+b); end endfunction assign c = myfunction (a,b);

endmodule
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Function Examples Parity Generator

module parity; reg [31:0] addr; reg parity; initial begin end function calc_parity; input [31:0] address; begin calc_parity = ^address; end endfunction endmodule always @(addr) begin parity = calc_parity(addr); $display("Parity calculated = %b",calc_parity(addr) ); end

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Function Examples Controllable Shifter

module shifter; `define LEFT_SHIFT 1'b0 `define RIGHT_SHIFT 1'b1 reg [31:0] addr, left_addr, right_addr; reg control; initial begin end function [31:0] shift; input [31:0] address; input control; begin shift = (control==`LEFT_SHIFT) ?(address<<1) : (address>>1); end endfunction endmodule

always @(addr) begin left_addr =shift(addr, `LEFT_SHIFT); right_addr =shift(addr,`RIGHT_SHIFT); 2014 Tasks and Functions end

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Automatic (Recursive) Functions:

Functions are normally used non-recursively. If a function is called concurrently from two locations, the results are non-deterministic because both calls operate on the same variable space. However, the keyword automatic can be used to declare a recursive (automatic) function where all function declarations are allocated dynamically for each recursive calls. Each call to an automatic function operates in an independent variable space. Automatic function items cannot be accessed by hierarchical references. Automatic functions can be invoked through the use of their hierarchical name.

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// Define the function function automatic integer factorial; input [31:0] oper; begin if (oper >= 2) factorial = factorial (oper -1) * oper; //recursive call else factorial = 1 ; end endfunction // Call the function integer result; initial begin result = factorial(4); // Call the factorial of 4 $display("Factorial of 4 is %d", result); //Displays 24 end endmodule
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Constant Functions:
A constant function is a regular Verilog HDL function, can be used instead of constants. module ram (...); parameter RAM_DEPTH = 256; input [clogb2(RAM_DEPTH)-1:0] addr_bus; //width of bus computed //by calling constant //function defined below //Result of clogb2 = 8 //input [7:0] addr_bus; //Constant function function integer clogb2(input integer depth); begin for(clogb2=0; depth >0; clogb2=clogb2+1) depth = depth >> 1; end endfunction endmodule 2014 Tasks and Functions

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Signed Functions:
Signed functions allow signed operations to be performed on the function return values.

module top; -//Signed function declaration //Returns a 64 bit signed value function signed [63:0] compute_signed(input [63:0] vector); -- -endfunction -//Call to the signed function from the higher module if(compute_signed(vector) < -3) begin -end -2014 Tasks and Functions endmodule

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