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Introduction Role of VLSI In digital circuits Gaps in present Study Objectives Methodology
INTRODUCTION
GATE DIFFUSION INPUT (GDI)
It is a new technique of low power digital combinational circuit design. This technique allows reducing power consumption, propagation delay, area of digital circuits while maintaining low complexity design . GDI allows implementation of wide range of complex logic functions using only two transistors. Basic GDI cell:
2.The second failure of high-power circuits relates to the increasing popularity of portable electronic devices. Laptop computers, portable video players and cellular phones all use batteries as a power source. To extend the battery life, low power operation is desirable in integrated circuits.
Mod-GDI CELL
Modified GDI cell contains a low voltage terminal SP configured to be connected to high constant voltage (i.e. supply voltage) a high voltage terminal SN configured to be connected to a low constant voltage(i.e. ground). Including terminals these ensures that the Mod-GDI cell can be implemented with all current CMOS technologies
OR AND F1 F2 MUX
2 2 2 2 2
2 2 2 2 2
6 6 6 6 12
NAND
NOR XOR XNOR
.520
.540 .545 .540
.242
.280 .362 .363
.280
.300 .567 .567
4
4 4 4
4
4 3 3
4
4 16 16
.657
.680 1.48 1.50
.54
.654 1.23 1.23
.64
.75 1.5 1.5
OBJECTIVES
1. To design an area efficient and low power digital circuit by using GDI technique. 2. To design logic gates that that has less transistor count and consume less power.
3. To design radix 4 booth multiplier using these gates . 4. To achieve low power dissipation and less delay for high performance of system. 5. To achieve reduction in sub threshold and gate leakage current of designed circuit.
METHODOLOGY
1. Study of GDI techniques for the design of a low power digital circuit. 2. Comparison between these techniques is done and best technique is selected which is MGDI. 3. Logic gates are designed using MGDI technique. 4. Radix 4 booth multiplier is designed using MGDI. 4. Various parameters like area count, power dissipation and delay of gates and multiplier are calculated.
5. Design and simulation of all the circuits have been performed by TANNER
using TSMC BSIM .180m technologies.
Publication
I have written a review paper on COMPARATIVE PERFORMANCE ANALYSIS OF VARIOUS LOW POWER GDI TECHNIQUES FOR DIGITAL CIRCUITS
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