Low Power Vlsi

LOW POWER VLSI
SEMINAR
BY
GOWRAV L (1MS13LVS03)
TOPIC COVERAGE (CONTENTS)

4.1.3
- Circuit Activity Driven Architectural Transformations
4.1.4
- Architecture-Driven Voltage Scaling
MSRIT _LPVLSI Subject Seminar
28-04-2014
INTRO
Filters in DSP circuits represented by state equations
-Architectural transforms can be applied on these
Roy and Chatterjee proposed heuristic transforms

-These transforms use commutative and associative laws of linear operations on linear time invariant digital circuits.
http://dl.acm.org/citation.cfm?id=164923
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IMPLEMENTATION TECHNIQUE
The filter can be implemented using either word-parallel or bitserial arithmetic.
Word - Parallel
In the word- parallel case, each signal (arc) of the data flow graph of Figure 4.7 represents W bits of data comprising a data word. The W bits {bw, bw-1,.. ...,b1} are fed in parallel to the respective adders and multipliers.
MSRIT _LPVLSI Subject Seminar 28-04-2014 5
8 8 8 8
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CONT.
The delays are designed to hold W bits in parallel. At time (t + 1) next frame, let z out of W bits have
different logic values than at time t.
Signal activity is defined as the ratio of z over W

and is given by (t)= z/W
The variable (t) is a random variable for different values of t and represents a stochastic process.
The authors define the average activity (t, t + N) of a signal over N consecutive time frames as
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FOR SERIAL-BIT IIR

In case of bit-serial arithmetic, the bit values of the data word are transmitted serially over a single data line over consecutive time steps. Thus it is not inter-word differences in bit values, but intra-word bit differences that cause node activity.
FORMULAE
Over large values of N show that the average activity factor
remains constant, showing that the stochastic process is strict sense stationary.
Average Power for this case
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CASE 1
The architectural transforms on the DSP filters are based on the following observations obtained through extensive simulation
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Consider a word- parallel computation tree I inputs (i1, i2,---,

ii )and output rational constants.
For simplicity, let I = 2L 1, where L is the number of levels in a perfectly balanced adder tree, as shown in Figure 4.8. If input values of the tree are mutually independent, then:
CASE 2 - LINEAR ARRAY ADDERS
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CONCLUSION
Note that no assumptions were made
regarding the implementation details of the adders or the multipliers.
Assuming that the capacitances at the

internal nodes are all equal, improvement of
up to 23% in power dissipation can be

achieved.
END OF 4.1.3
References :
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4.1.4 - ARCHITECTURE-DRIVEN VOLTAGE SCALING
P=
2 CV f
large improvement in power dissipation can be obtained if the supply voltage is scaled down, as Vdd appears as a square term in the expression for average power dissipation. one immediate side effect is the increase in circuit delay due to the voltage reduction.
PROBLEM -- NON LINEARITY

In the submicrometer range the interconnect capacitances do not scale proportionately and can become dominant. Hence, it is worth looking at architectural transformations to compensate for the delay to achieve lower power dissipation by scaling down the supply voltage SOLUTION -- PARALLEL OR PIPELINED ARCHITECTURE.
CASE
P=
2 CV f
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Vdd scaled down from 5 to 2.9 V
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RESULTS
This method of using parallelism to reduce power has the overhead of more than twice the area and is not suitable for area constrained designs.
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ALTERNATE APPROACH PIPELINING
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EFFECTS
With additional pipeline latch (Figure 4.12, the critical path becomes max[Tadder, Tcomparator ], allowing the adder and the comparator to operate at a slower speed. If one assumes the two delays to be equal, the supply voltage can again be reduced from 5 to 2.9 V, the voltage at which the delay doubles, with no loss in throughput. Due to the addition of the extra latch, if the effective capacitance increases by a factor of 1.15, then
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RESULTS AND CONCLUSION

As an added bonus in pipelining, increasing the levels of pipelining has the effect of reducing logic depth and hence power contributed due to hazards. An obvious extension is to use a combination of pipelining and parallelism to obtain area and power constrained design.
References : LOW-POWER CMOS VLSI CIRCUIT DESIGN > Kaushik Roy Sharat C. Prasad
THANK YOU

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LOW POWER VLSI

TOPIC COVERAGE (CONTENTS)

- Architecture-Driven Voltage Scaling

MSRIT _LPVLSI Subject Seminar

Roy and Chatterjee proposed heuristic transforms

MSRIT _LPVLSI Subject Seminar

MSRIT _LPVLSI Subject Seminar

MSRIT _LPVLSI Subject Seminar

Signal activity is defined as the ratio of z over W

MSRIT _LPVLSI Subject Seminar

FOR SERIAL-BIT IIR

Average Power for this case

MSRIT _LPVLSI Subject Seminar

Consider a word- parallel computation tree I inputs (i1, i2,---,

CASE 2 - LINEAR ARRAY ADDERS

MSRIT _LPVLSI Subject Seminar

Assuming that the capacitances at the

up to 23% in power dissipation can be

MSRIT _LPVLSI Subject Seminar

4.1.4 - ARCHITECTURE-DRIVEN VOLTAGE SCALING

PROBLEM -- NON LINEARITY

MSRIT _LPVLSI Subject Seminar

Vdd scaled down from 5 to 2.9 V

MSRIT _LPVLSI Subject Seminar

MSRIT _LPVLSI Subject Seminar

ALTERNATE APPROACH PIPELINING

MSRIT _LPVLSI Subject Seminar

MSRIT _LPVLSI Subject Seminar

RESULTS AND CONCLUSION

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