DISTRIBUTED PROCESSING UNIT DPU4F DPU IS THE HARDWARE PROCESSING ENGINE OF THE maxDNA DCS.

S. IT PERFORMS PRIMARY DATA ACQUISITION , CONTROL & DATA PROCESSING FUNCTIONS. MOUNTED IN A SINGLE SLOT OF THE 8 PAC RACK. OPERATES IN CONJUNCTION WITH THE I/O MODULES. CAPABLE OF COMMUNICATING WITH OTHER DEVICES SUCH AS PLCs. CAPABLE OF BEING CONFIGURED AS A BACKUP PAIR. PROVIDES CONNECTIVITY TO MAXNET & RESIDES AS A STATION ON THE MAXNET ALONG WITH THE I/O MODULES. ON THE MAXNET EACH DPU/DPU PAIR IS IDENTIFIED WITH A UNIQUE ETHERNET IP ADDRESS.

DISTRIBUTED PROCESSING UNIT DPU4F SCANS AND PROCESSES INFORMATION FOR USE BY OTHER DEVICES IN THE maxDNA SYSTEM. IT PERFORMS : CALCULATIONS & ALARMING. LOGGING OF SOE AT 1 ms RESOLUTION. ACQUISITION OF TREND INFORMATION. CONTINUOUS SCANNING OF I/O MODULES. EXECUTION OF CONTROL ALGORITHMS(CONFIGURATIONS) FOR PROCESS CONTROL & DATA ACQUISITION.

DPU4F- MAIN FEATURES

MUST BE MOUNTED IN THE LEFT MOST POSITION OF THE maxPAC RACK TO ALLOW FOR BEST AIRFLOW. WHEN USING A SECOND DPU , IT MUST BE MOUNTED VERTICALLY BENEATH THE PRIMARY TO ALLOW FOR CONNECTION OF THE BACKUP CABLE. EACH DPU/DPU PAIR CAN CONTROL UPTO MAXIMUM OF 60 I/O MODULES & ALLOWS A I/O BUS LENGTH OF 30 FEET. SITS ON MAXNET THRODUAL ETHERNET PORTS(10/100 MBPS). OPTIONALLY CONTAINS A SERIAL PORT & IRIG-B INTERFACE. DPU CAN SYNCHRONIZE TO SATELLITE TIME THROUGH IRIG-B INTERFACE.INTERFACE IS AVAILABLE ON THE FRONT PANEL THRO A BNC CONNECTOR. TIMING CAN BE TRANSMITTED TO ALL STATIONS ON THE maxNET. OPTIONALLY CONTAINS A RS232 PORT ON THE FRONT PANEL FOR INTERFACING TO EXTERNAL PLCS.

DISTRIBUTED PROCESSING UNIT --DPU4F FRONT PANEL FEATURES

DPU 4F MODEL NUMBERS

PDP401 --- DPU 4F PRIMARY PDP403 --- DPU 4F SECONDARY (WITH BACKUP CABLE) PDP406 --- DPU 4F WITH IRIG , PRIMARY PDP408 --- DPU 4F WITH IRIG , SECONDATY(WITH BACKUP CABLE)

DPU 4F -- SPECIFICATIONS

COMPACT FLASH
ON BOARD

REGULATORS

NET A CONTR

ETHERNET
CONTROLLER

BIOS FLASH

5V/3.3V/2.1V

24V IN

IDE BUS NET B CONTR

ETHERNET
CONTROLLER

I/O BACKPLANE

PCI BUS PCI INTERFACE CHIP

SHARED RAM FPGA

SHARED RAM

BACK UP CONTR

ETHERNET CONTROLL ER

CONTROL PROCESSOR

IOM PROCESSOR

(CP)
IRIG FRONT END (OPTIONAL)
MEMORY BUS

(IOM)
IOM FPGA SDRAM

I/O BUS

DPU 4F BLOCK DIAGRAM

DPU4F- HARDWARE/SOFTWARE FEATURES

CONTROL PROCESSOR (CP)- AMD GEODE -300MHZ IOM PROCESSOR FOR SCANNING I/O (IOM) - 68332 MOTOROLA MICROCONTROLLER. CONTAINS A 64MB/128MB COMPACT FLASH WHICH CARRIES THE DPU INITIALISATION INFORMATION & THE FIRMWARE FILES. 128MB OF DRAM. UPTO 8500 FUNCTION BLOCKS CAN BE EXECUTED IN THREE DIFFERENT TIME CLASSES. (10ms to 1/2s) RUNS WINDOWS CE.NET RTOS BUILT IN SOE WITH 1mS RESOLUTION.

DPU4F FRONT PANEL FEATURES

DPU FRONT PANEL CONTROLS & FEATURES

MODE SWITCH maxNET INTERFACE PORTS 16 POSITION ROTARY SWITCH. DETERMINES THE OPERATIONAL MODE OF THE MODULE. DUAL ETHERNET 10/100 BASE-T PORTS. PROVIDES CONNECTIVITY TO THE maxNET. (REDUNDANT --- NET A & NET B) REPORT THE STATUS OF THE maxNET NETA & NETB LINKS. A 100MBPS ETHERNET INTERFACE IS PROVIDED TO PASS DATABASE INFORMATION TO A HOT STANDBY DPU INDICATES REDUNDANY STATUS OF DPUS CONFIGURED AS A BACKUP PAIR. INDICATES OPERATIONAL STATE OF THE IOM PROCESSOR. INDICATES STATUS OF THE I/O BUS TRANSACTIONS REPORTS THE HEALTH OF THE CONTROL PROCESSOR

NETWORK STATUS LEDs BACKUP PORT

BACKUP LED IOM STATUS LED I/O STATUS LED CP STATE LED

STATE LED

REPORTS THE CURRENT CONTROL STATE OF THE DPU.

DPU FRONT PANEL CONTROLS & FEATURES

FRONT PANEL FEATURE FUNCTION

RESET BUTTON
TAKEOVER BUTTON SERIAL PORT (OPTIONAL) IRIG-B PORT (OPTIONAL)

PRESSING THIS BUTTON WILL CAUSE THE DPU TO STOP CONTROLLING & GO THROUGH A RESET CYCLE.
PRESSING THIS BUTTON WILL CAUSE A PREVIOUSLY INACTIVE DPU TO GO ACTIVE. OPTIONAL RS232 SERIAL PORT WITH RJ45 CONNECTOR FOR INTERFACING WITH EXTERNAL PLC TYPE DEVICES. BNC CONNECTOR WHICH SUPPORTS AN INTERFACE TO A GPS RECIEVER. THIS OPTION ALLOWS TIME SYNCHRINISATION TO GLOBAL TIME.

DPU4F MODE SWITCH DEFINITIONS

DPU4F MODE SWITCH DEFINITIONS (cont)

LED STATUS DURING NORMAL DPU OPERATION

DPU4F- COMPACT FLASH MEMORY

THE DPU 4F USES A COMPACT FLASH FOR STORING ALL SOFTWARE & CONFIGURATION INFORMATION. IT IS NON-VOLATILE & CAN BE MOVED FROM ONE DPU TO ANOTHER. THE COMPACT FLASH CONTAINS WIN CE .NET OS., IOM FIRMARE , FIRMWARE FOR SHARED MEMORY FPGA , FIRMEARE FOR IOM FPGA, IOM DIAGNOSTIC CODE ,BIOS FIRMWARE & THE DPU INITIALIZATION FILE. THE DPU INITIALIZATION FILE CONTAINS THE DPU NAME ,IP ADDRESS & OTHER CONFIGURATION INFORMATION. CHANGING THE IP ADDRESS & DPU NAME IN THE INITIALIZATION FILE CAN BE ACCOMPLISHED THRO THE DPU4F SETUP UTILITY WITH THE DPU IN MODE C.

REDUNDANT DPU OPERATION

IN REDUNDANT OPERATION TWO DPUS ARE CONNECTED TO FORM A BACKUP PAIR. ONE DPU IS DESIGNATED AS THE PRIMARY AND THE OTHER DPU , THE SECONDARY. THE IP ADDRESS OF THE SECONDARY DPU IS ONE NUMBER GREATER THAN THE ADDRESS OF THE PRIMARY DPU. THE PRIMARY IS ALWAYS AN EVEN ADDRESS WHILE THE SECONDARY IS AN ODD ADDRESS. INFORMATION BETWEEN THE BACKUP PAIR IS EXCHANGED BY MEANS OF A 100MBPS ETHERNET INTERFACE. A CAT5e ETHERNET CABLE IS USED TO CONNECT THE TWO DPUS TOGETHER. PROCESS CONTROL CAN BE TRANSFERRED AUTOMATICALLY(FAILOVER) OR MANUALLY BETWEEN PRIMARY & SECONDARY. AUTOMATIC FAILOVER CAN OCCUR FROM EITHER THE PRIMARY DPU TO THE SECONDARY DPU OR FROM THE SECONDARY TO THE PRIMARY BASED ON THE HEALTH OF BOTH. ALSO DPU CAN BE COMMANDED TO TAKEOVER MANUALLY BY PRESSING THE TAKEOVER BUTTON ON THE FRONT PANEL OF THE MODULE.

DPU4F-module
OPERATOR INTERFACE