DSP OVERVIEW

DSPs are like traditional embedded

microprocessors

DSPs are designed to meet sophisticated signal
processing algorithms

DSPs are used in drives, audio & video
applications, image applications, bio medical,
industrial automations etc.,
ADVANTAGES OF DSP
Easy to change applications

Better control & accuracy

Easy to execute complex algorithms like svpwm,
vector control , dtc etc.,

Compact in size (ic)

Cost effective (ic) for particular applications.


DSP LEADING MANUFACTURERS
Texas instruments

Analog devices

Motorola
TEXAS INSTRUMENTS DSP FAMILY
TMS320C2000

C24x, C28x
TMS320C5000

C54x,C55x
TMS320C6000

C62x,C64x,C67x
TMS320 DEVICE NOMENCLATURE
DSP BASED MOTOR CONTROL
TMS320C2000 series offers various processors for motor
control applications

Based on the requirements user can choose the
following processors

TMS320C240

TMS320LF2407

TMS320LF2812
LF2407 KEY FEATURES
3.3v operating volts

16 bit fixed point processor with 144 pins

40MHz operating frequency

32KWord FLASH memory, 2.5 K Word RAM

40 general-purpose I/O (GPIO) lines

Event manager


10 bit, 16 channel ADC with 500ns as conversion time

Serial communication interface (SCI)

Serial peripheral interface (SPI)

Watchdog timer

In-built space vector hardware

TMS320LF2407 ARCHITECTURE
CENTRAL PROCESSING UNIT
A 32-bit central arithmetic logic unit (CALU)

A 32-bit accumulator

Data-scaling shifters

A 16-bit X 16-bit multiplier

A 32-bit product register

8 auxiliary registers and an auxiliary register arithmetic unit
MEMORY
544 words * 16 bits of on-chip data/program dual-
access RAM

32K words * 16 bits of on-chip program
Flash EEPROM

2K words * 16 bits of single-access RAM

External memory interface module

PLL CLOCK MODULE
PLL Clock Module provides all of the clocks required
for the entire device.

CPUCLK This is the highest frequency clock
provided by the module and is used by the CPU, all
memories and any peripherals tied directly to the
CPUs buses, including an external memory interface
if used.

SYSCLK This clock is a half or a quarter the rate of
CPUCLK. It is used to clock all the peripherals on the
TI peripheral bus.

WDCLK This is the low power clock used by the
watchdog timer/real- time interrupt module.
WATCHDOG TIMER MODULE
Internal 8 bit re-settable up counting timer, that
reset the system if software fails to operate
properly.

If the software goes into an improper loop, or if
the CPU becomes temporarily disrupted, the WD
timer overflows to assert a system reset.

The watchdog increases the reliability of the
CPU, thus ensuring system integrity.
SERIAL COMMUNICATION INTERFACE MODULE
The programmable SCI module supports digital
communications between the CPU and other
asynchronous peripherals.

To ensure data integrity, the SCI checks data that
has been received for break detection, parity,
overrun, and framing errors.

The speed of the bit rate (baud) is programmable to
over 64K different speeds through a 16-bit baud-
select register.

SERIAL PERIPHERAL INTERFACE MODULE
The SPI is a high-speed synchronous serial input/
output (I/O) port that allows a serial bit stream of
programmed length (one to eight bits) to be shifted
into and out of the device at a programmed bit-
transfer rate.

The SPI is normally used for communications
between the DSP controller and external peripherals
or another controller.

SPI applications include external I/O or peripheral
expansion via devices such as shift registers,
display drivers, and analog-to-digital converters
(ADCs).

DIGITAL I/O MODULE
The digital I/O ports module provides a
flexible method for controlling both
dedicated I/O and shared pin functions

The LF2407 has a total of 40 shared I/O lines

I/O ports can be used as i/o lines or as pwm
lines
EVENT MANAGER (EV) MODULE
The EV module provides functions and features that are required for motor
control applications

LF2407 has two event managers EVA & EVB

Features:

2 general-purpose (GP) timers

3 compare units

3 capture units

quadrature encoder pulse(QEP) circuit

space vector pwm circuits

dead band generation units

output logic circuits
EV BLOCK DIAGRAM
PWM OUTPUT
EVENT MANAGER REGISTERS
EVENT MANAGER TIMER REGISTERS

GPTCONA - General purpose timer control register
T1CNT - Timer1 counter register
T1CMPR - Timer1 compare register
T1PR - Timer1 period register
T1CON - Timer1 control register

EVENT MANAGER COMPARE CONTROL REGISTERS

COMCONA - Compare control register
ACTRA - Action control register
DBTCONA - Dead-band control register
CPMR1 - Compare register1
CMPR2 - Compare register2
CMPR3 - Compare register3

SPACE VECTOR PWM MODULE
The EV module has built-in hardware to
generate svpwm

Software is used to generate svpwm outputs

CAPTURE & QEP UNITS
The capture & QEP units can be used to
interface with an optical encoder to get speed
information from the rotating machine

Capture unit is used to sense the actual speed of
the machine

QEP is used to find the direction of rotation of
the machine


ANALOG TO DIGITAL CONVERTER
Features:
10-bit ADC core with built-in S/H circuit

Fast conversion time of 500ns

16 multiplexed analog input

Two independent 8 state sequencer can be
operated in dual-sequencer or cascaded mode

16 result registers to store the digital values
ADC BLOCK DIAGRAM
ADC CONTROL REGISTERS
ADCTRL1 - Adc control register1

ADCTRL2 - Adc control register2

MAXCONV - Maximum conversion reg

CHSELSEQn - Channel select registers

RESULTn - Adc result registers
PROGRAM MEMORY ADDRESS FOR TRAINER KIT

Starting
address
Ending
address
Description
Memory
Type
0000 BFFF
ASSEMBLER,
DISASSEMBLER,
SERIAL MONITOR
PROGRAM AREA
EEPROM
C000
FFFF
USER
PROGRAM
MEMORY
AREA
RAM
LF2407 DATA MEMORY
Total memory = 0000h FFFFh (64KW)

Total no. pages = 200h

Every page contains 80h locations

Page 0 = 0h * 80h = 0000 to 007F

Page 1 = 1h * 80h = 0080 to 00FF

. . . . . . .
. . . . . . .
. . . . . . .

Page 100 = 100h * 80h = 8000 to 807F

Page 1FF = 1FFh * 80h = FF80 to FFFF

DATA MEMORY ADDRESS FOR TRAINER KIT

Starting
address
Ending
address
Description
Memory
Type
0000 7FFF
8000
FFFF
RAM
ON-CHIP RAM
USER DATA
MEMORY AREA
RAM
ASSEMBLEY LANGUAGE PROGRAMS
ADDI TI ON
.TEXT
.MMREGS
START:
LDP #100H
LACC 0H
ADD 1H
SACL 2H
H: B H

Input:
8000 3333
8001 2222
Output:8002 - 5555
.TEXT
.MMREGS
START:
LDP #100H
LACC #3333H
ADD #2222H
SACL 0H
H: B H

Output:
8000 5555



SIMPLE PROGRAM FOR PWM GENERATION
.include 2407regs.h
.text
Start:
LDP #232
SPLK #2000,T1PR
SPLK #1000,T1CMPR
SPLK #1000,T2CMPR
SPLK #1000,T3CMPR
SPLK #0999H,ACTRA
SPLK #8200H,COMCONA
SPLK #0000,T1CNT
SPLK #0000,T2CNT
SPLK #0000,T3CNT
SPLK #0802H,T1CON
SPLK #0842H,T1CON
END B END